| Patent application number | Description | Published |
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| 20080246015 | METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT - Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described. | 10-09-2008 |
| 20080258291 | Semiconductor Packaging With Internal Wiring Bus - A packaged semiconductor includes inner bond fingers, at least first and second semiconductor dies, and an interposer. The packaged semiconductor further includes wiring between the first and second semiconductor dies and the inner bond fingers, wiring between the interposer and the inner bond fingers, and wiring between the interposer and the first and second semiconductor dies. The wiring between the interposer and the first and second semiconductor dies thereby reduces the count of inner bond fingers needed for the wiring between the first and second semiconductor dies and the inner bond fingers. The interposer further provides indirect access to the inner bond fingers when the inner bond fingers are inaccessible by the first and second semiconductor dies. | 10-23-2008 |
| 20090017593 | METHOD FOR SHALLOW TRENCH ISOLATION - Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described. | 01-15-2009 |
| 20090212410 | STACK DIE PACKAGES - An integrated circuit package includes a substrate comprising a first contact. A first integrated circuit mechanically attached to the substrate. The first integrated circuit comprising a second contact. A first redistribution layer arranged on the first integrated circuit. The first redistribution layer includes a trace coupled to the second contact. A first wire connects the first contact to the second contact. A flip-chip integrated circuit comprises a third contact connected to the trace by a conductive bump. A second integrated circuit mechanically coupled to the flip-chip integrated circuit. The second integrated circuit comprises a fourth contact. A second wire connects the fourth contact to at least the second contact or the first contact. | 08-27-2009 |
| 20100140760 | ALPHA SHIELDING TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure provide an apparatus including a semiconductor die having a plurality of integrated circuit devices, a pad structure electrically coupled to at least one integrated circuit device of the plurality of integrated circuit devices via an interconnect layer, an electrically insulative layer disposed on the interconnect layer, a first shielding structure disposed in the electrically insulative layer and electrically coupled to the pad structure, an under-ball metallization (UBM) structure electrically coupled to the first shielding structure, and a solder bump electrically coupled to the UBM structure, the solder bump comprising a solder bump material capable of emitting alpha particles, wherein the first shielding structure is positioned between the solder bump and the plurality of integrated circuit devices to shield the plurality of integrated circuit devices from the alpha particles. Other embodiments may be described and/or claimed. | 06-10-2010 |
| 20100173452 | METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT - Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described. | 07-08-2010 |
| 20100301467 | WIREBOND STRUCTURES - Embodiments of the present disclosure provide an apparatus comprising a semiconductor die, a bond pad formed on the semiconductor die, the bond pad comprising aluminum (Al), a bonding material comprising gold (Au) coupled to the bond pad, the bonding material covering at least a portion of the bond pad, and a wire coupled to the bonding material, the wire comprising copper (Cu). Other embodiments may be described and/or claimed. | 12-02-2010 |
| 20110121444 | EMBEDDED CHIP PACKAGES - Embodiments of the present disclosure provide configurations for a semiconductor package and associated methods of fabricating the semiconductor package. A method of fabricating a semiconductor package includes attaching a semiconductor die to a first substrate, attaching a second substrate to the first substrate, wherein the semiconductor die is embedded in between the first substrate and the second substrate, and forming an electrically insulative structure to substantially encapsulate the semiconductor die, wherein forming the electrically insulative structure is performed subsequent to the second substrate being attached to the first substrate. Additional embodiments may be described and/or claimed. | 05-26-2011 |
| 20110148312 | INTEGRATED BUCK POWER SUPPLY ARCHITECTURES FOR LED-BASED DISPLAYS - A system includes a plurality of light emitting diodes (LEDs) and a control module configured to generate pulse width modulated (PWM) pulses to drive the LEDs. The LEDs and the control module are integrated in an integrated circuit (IC) package. | 06-23-2011 |
| 20110169163 | ATTACHING PASSIVE COMPONENTS TO A SEMICONDUCTOR PACKAGE - Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed. | 07-14-2011 |
| 20110175218 | PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE - Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed. | 07-21-2011 |
| 20110180913 | METHOD OF STACKING FLIP-CHIP ON WIRE-BONDED CHIP - Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for stacking chips. A first chip may be mounted on a substrate, wherein an active surface of the first chip faces away from the substrate, and wherein the first chip includes a plurality of bump pads located on the active surface of the first chip, and a wire may bond a first bump pad of the plurality of bump pads to the substrate. An intermediate layer may be disposed on at least a portion of the active surface of the first chip, and a via within the intermediate layer may extend to a second bump pad of the plurality of bump pads. A second chip may be disposed on the intermediate layer, wherein an active surface of the second chip faces towards the substrate, and wherein the second chip includes a third bump pad (i) located on the active surface of the second chip and (ii) aligned with the via formed in the intermediate layer. A corresponding bump may be disposed on one or more of (i) the second bump pad located on the active surface of the first chip and (ii) the third bump pad located on the active surface of the second chip, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad. Other embodiments are also described and claimed. | 07-28-2011 |
| 20110186960 | TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed. | 08-04-2011 |
| 20110186992 | RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES - Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed. | 08-04-2011 |
| 20110186998 | RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed. | 08-04-2011 |
| 20110227223 | EMBEDDED DIE WITH PROTECTIVE INTERPOSER - Embodiments of the present disclosure provide a substrate having (i) a first laminate layer, (ii) a second laminate layer, and (iii) a core material that is disposed between the first laminate layer and the second laminate layer; and a die attached to the first laminate layer, the die having an interposer bonded to a surface of an active side of the die, the surface comprising (i) a dielectric material and (ii) a bond pad to route electrical signals of the die, the interposer having a via formed therein, the via being electrically coupled to the bond pad to further route the electrical signals of the die, wherein the die and the interposer are embedded in the core material of the substrate. Other embodiments may be described and/or claimed. | 09-22-2011 |
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| 20100162954 | Integrated facility and process chamber for substrate processing - In accordance with some embodiments described herein, a process module facility is provided, comprising: at least one process chamber carried in frame, a subfloor adjacent the process module, a stationary pump and electrical box positioned atop the subfloor; and gas control lines and vacuum exhaust lines housed within the subfloor and coupled the process chamber. The process module facility may be integrated with a larger system for processing substrates which includes two or more process module facilities, a substrate handling robot, a load lock chamber, and a transverse substrate handler. The transverse substrate handler includes mobile transverse chambers configured to convey substrates to process modules, wherein each mobile transverse chamber is configured to maintain a specified gas condition during the conveyance of the substrates. The transverse substrate handler further includes a rail for supporting the mobile transverse chambers, wherein the rail is positioned adjacent to entry of the process modules, and drive systems for moving the mobile transverse chambers on the rail. | 07-01-2010 |
| 20100162955 | Systems and methods for substrate processing - In accordance with some embodiments described herein, a system for processing substrates includes two or more process modules, a substrate handling robot, a load lock chamber, and a transverse substrate handler. The transverse substrate handler includes mobile transverse chambers configured to convey substrates to process modules, wherein each mobile transverse chamber is configured to maintain a specified gas condition during the conveyance of the substrates. The transverse substrate handler further includes a rail for supporting the mobile transverse chambers, wherein the rail is positioned adjacent to entry of the process modules, and drive systems for moving the mobile transverse chambers on the rail. | 07-01-2010 |
| 20100167503 | Methods and systems of transferring, docking and processing substrates - In accordance with some embodiments described herein, a method for transferring a substrate to two or more process modules is provided, comprising loading at least one substrate into one or more mobile transverse chambers, the mobile transverse chambers being carried on a rail positioned adjacent to the two or more process modules, and wherein each mobile transverse chamber is configured to maintain a specified gas condition during conveyance of the substrate. One or more drive systems are actuated to propel at least one of the one or more mobile transverse chambers along the rail. The at least one mobile transfer chamber docks to at least one of the process modules, and the substrate is conveyed from the mobile transverse chamber to the at least one process modules. | 07-01-2010 |
| 20100173439 | Methods and systems of transferring a substrate to minimize heat loss - A method of transferring one or more substrates between process modules or load lock stations while minimizing heat loss is provided. In some embodiments the method comprising the steps of: identifying a destination location D1 for a substrate S1 present at an initial processing location P1; if the destination location D1 is occupied with a substrate S2, maintaining the substrate S1 at the initial processing location P1; and if the destination location D1 is available, transferring the substrate S1 to the destination location D1. In accordance with additional embodiments, the method is carried out on a system for processing substrates which includes two or more process modules, a substrate handling robot, a load lock chamber, and a transverse substrate handler. The transverse substrate handler includes mobile transverse chambers configured to convey substrates to process modules, wherein each mobile transverse chamber is configured to maintain a specified gas condition during the conveyance of the substrates. The transverse substrate handler further includes a rail for supporting the mobile transverse chambers, wherein the rail is positioned adjacent to entry of the process modules, and drive systems for moving the mobile transverse chambers on the rail. | 07-08-2010 |
| 20110151119 | Methods and Systems of Transferring, Docking and Processing Substrates - In accordance with some embodiments described herein, a method for transferring a substrate to two or more process modules is provided, comprising loading at least one substrate into one or more mobile transverse chambers, the mobile transverse chambers being carried on a rail positioned adjacent to the two or more process modules, and wherein each mobile transverse chamber is configured to maintain a specified gas condition during conveyance of the substrate. One or more drive systems are actuated to propel at least one of the one or more mobile transverse chambers along the rail. The at least one mobile transfer chamber docks to at least one of the process modules, and the substrate is conveyed from the mobile transverse chamber to the at least one process modules. | 06-23-2011 |
| 20110217469 | Methods and Systems of Transferring, Docking and Processing Substrates - In accordance with some embodiments described herein, a method for transferring a substrate is provided. The method includes loading one or more substrates into a respective mobile chamber of one or more mobile chambers. The mobile chambers are movable on a first rail positioned adjacent to two or more process modules. Each mobile chamber is configured to maintain a specified gas condition. The respective mobile chamber is moved along the first rail. The respective mobile chamber is docked to a respective process module of the two or more process modules. At least one of the one or more substrates is conveyed from the respective mobile chamber to the respective process module. | 09-08-2011 |
