Patent application number | Description | Published |
20100321957 | STANDBY POWER METHOD AND APPARATUS FOR POWER MODULE APPLICATIONS - The present invention discloses a standby power saving method for power module applications, comprising the steps of: generating a mode signal according to voltage comparison of a feedback signal and a threshold voltage, wherein the mode signal has a normal mode state and a standby mode state; generating a pulse signal according to the mode signal, wherein the pulse signal has a normal PWM mode responsive to the normal mode state of the mode signal, and a V | 12-23-2010 |
20110068751 | SAFETY CAPACITOR DISCHARGING METHOD AND APPARATUS FOR AC-TO-DC CONVERTERS - The present invention discloses a safety capacitor discharging method for AC-to-DC converters, wherein the AC-to-DC converters have a safety capacitor connected between two line voltages, the method comprising the steps of: detecting at least one line voltage to generate a line-off signal, wherein the line-off signal is at a first state when the peak voltage of the at least one line voltage is above a reference voltage, and the line-off signal is at a second state when the peak voltage of the at least one line voltage is below the reference voltage; and performing discharge of the safety capacitor by generating a conduction path between two plates of the safety capacitor when the line-off signal is at the second state. The present invention also provides a safety capacitor discharging apparatus for AC-to-DC converters. | 03-24-2011 |
20110127978 | PWM CONTROLLER WITH LOW UVLO VOLTAGE - The present invention discloses a PWM controller with low UVLO voltage for switching power applications, having a power supply end coupled to a main input voltage via a resistor and coupled to a ground via a capacitor, and an output end coupled to the gate terminal of a primary side transistor requiring a minimum gate voltage, the PWM controller comprising: a UVLO unit; used for performing a hysteresis comparison of a supply voltage at the power supply end with a UVLO_ON voltage and a UVLO_OFF voltage to generate a control signal, wherein the UVLO_OFF voltage can be as low as the minimum gate voltage; a PWM unit, actuated by the control signal to deliver a PWM signal; and a driving stage, comprising a PMOS transistor having a gate coupled to the PWM signal, a source coupled to the supply voltage and a drain coupled to the output end. | 06-02-2011 |
Patent application number | Description | Published |
20100234975 | ADVANCED PROCESS CONTROL FOR GATE PROFILE CONTROL - A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; performing a plurality of processes to form a gate stack over the substrate, wherein the gate stack comprises a gate layer; measuring a grain size of the gate layer after at least one of the plurality of processes; determining whether the measured grain size is within a target range; and modifying a recipe of at least one of the plurality of processes if the measured grain size of the gate layer is not within the target range. | 09-16-2010 |
20110108940 | METHOD OF FABRICATING BACKSIDE-ILLUMINATED IMAGE SENSOR - Provided is a method of fabricating a backside illuminated image sensor that includes providing a device substrate having a frontside and a backside, where pixels are formed at the frontside and an interconnect structure is formed over pixels, forming a re-distribution layer (RDL) over the interconnect structure, bonding a first glass substrate to the RDL, thinning and processing the device substrate from the backside, bonding a second glass substrate to the backside, removing the first glass substrate, and reusing the first glass substrate for fabricating another backside-illuminated image sensor. | 05-12-2011 |
20130001725 | METHOD OF FABRICATING BACKSIDE-ILLUMINATED IMAGE SENSOR - Provided is a method of fabricating a backside illuminated image sensor that includes providing a device substrate having a frontside and a backside, where pixels are formed at the frontside and an interconnect structure is formed over pixels, forming a re-distribution layer (RDL) over the interconnect structure, bonding a first glass substrate to the RDL, thinning and processing the device substrate from the backside, bonding a second glass substrate to the backside, removing the first glass substrate, and reusing the first glass substrate for fabricating another backside-illuminated image sensor. | 01-03-2013 |
20130093036 | METHOD OF FABRICATING BACKSIDE-ILLUMINATED IMAGE SENSOR - Provided is a method of fabricating a backside illuminated image sensor that includes providing a device substrate having a frontside and a backside, where pixels are formed at the frontside and an interconnect structure is formed over pixels, forming a re-distribution layer (RDL) over the interconnect structure, bonding a first glass substrate to the RDL, thinning and processing the device substrate from the backside, bonding a second glass substrate to the backside, removing the first glass substrate, and reusing the first glass substrate for fabricating another backside-illuminated image sensor. | 04-18-2013 |
Patent application number | Description | Published |
20120262421 | Optical Touchpad, Portable Electronic Device and Method thereof - Optical touchpad includes a light source for emitting light of a specific wavelength, a specific-light sensing array for sensing the specific light after being reflected by an instruction object for accordingly generating a specific-light sensing image, a proximity detector for determining an instruction distance between the instruction object and the optical touchpad according to the specific-light sensing image, and a motion detector for determining path of the instruction object and then outputting a motion signal according to the specific-light sensing image. When the instruction distance is greater than a predetermined value, the motion detector is turned off. | 10-18-2012 |
20130057516 | OPTICAL TOUCH-CONTROL SYSTEM WITH TRACK DETECTING FUNCTION AND METHOD THEREOF - The optical touch-control system processing track detection includes a light source for emitting a specific light; a sensing array for sampling the specific light reflected by an instruction object in a predetermined period of time for accordingly generating a first and a second sensing image signals; a motion detector for determining the track of the instruction object for outputting a motion vector signal according to the first and the second sensing image signals; and a processor for controlling movement of a target object according to the motion vector signal and the predetermined period of time; wherein the instruction object moves within a first zone of the sensing array. | 03-07-2013 |
20140092019 | OPTICAL NAVIGATION METHOD FOR DYNAMICALLY ADJUSTING SIZE OF IMAGE SENSING REGION AND RELATED APPARATUS THEREOF - An optical navigation method includes: detecting inertia of an image of a feature point; and determining an effective sensing region of an image sensing array according to the detected inertia for reducing power consumption. Besides, an optical navigation apparatus includes a detecting circuit and a determining unit. The detecting circuit is arranged for detecting a moving inertia of a feature point. The determining circuit is coupled to the detecting circuit, and arranged for determining an effective sensing region of an image sensing array according to the detected moving inertia for reducing power consumption. | 04-03-2014 |
20140095735 | COMMUNICATION METHOD APPLIED TO TRANSMISSION PORT BETWEEN ACCESS DEVICE AND CONTROL DEVICE FOR PERFORMING MULTIPLE OPERATIONAL COMMAND FUNCTIONS AND RELATED ACCESS DEVICE THEREOF - A communication method applied to a transmission port between an access device and a control device includes: encoding a specific command to generate mode data; generating output data according to content of the mode data and content of command data corresponding to the specific command; and transmitting the output data from one of the access device and control device to the other via the transmission port. The other device of the access device and control device is used for receiving the output data and decoding the mode data of the output data to generate a decoding result, and selecting the specific command from a plurality of operational commands for executing a communication function corresponding to the specific command according to the decoding result. | 04-03-2014 |
20140097330 | METHOD OF TESTING IMAGE SENSOR AND RELATED APPARATUS THEREOF - A method of testing an image sensor having a plurality of sensing units includes: utilizing the image sensor to generate a plurality of sensing results respectively corresponding to a plurality of captured images, wherein each sensing result includes a plurality of sensing values respectively generated by the sensing units; and generating a testing result which indicates a performance of the image sensor according to changing of the sensing results. | 04-10-2014 |
20140098021 | OPTICAL NAVIGATING APPARATUS AND COMPUTER READABLE MEDIA CAN PERFORM OPTICAL NAVIGATING METHOD - An optical navigating apparatus, which comprises: a light source, for illuminating a surface to generate an image; an image sensor, for catching pictures of the image; and a controller, for computing a first estimating speed of the optical navigating apparatus according to a first picture of the pictures and a second picture after the first picture. The controller controls at least one of parameters as following according to the first estimating speed: a non-illuminating frequency that the light source does not illuminate pictures after the second picture; a non-catching frequency that the image sensor does not catch pictures after the second picture; a computing frequency that the controller computes pictures after the second picture, which are caught by the image sensor; and a searching range for pictures after the second picture. | 04-10-2014 |
Patent application number | Description | Published |
20150064629 | MANUFACTURING METHOD FOR MICROLENSES - A manufacturing method of microlenses includes providing a substrate; forming a microlens material on the substrate; disposing a mask over the microlens material; performing an exposure process by a radiant beam emitted to the microlens material via the mask; performing a developing process on the microlens material; and forming microlenses by performing a reflow process on the microlens material. | 03-05-2015 |
20160027829 | Image Sensing Device and Method for Fabricating the Same - An image sensing device is provided. The image sensing device includes a substrate having a pixel array with a plurality of pixels. A light guide structure is disposed over the substrate, forming a plurality of light pipes and a plurality of reflecting portions surrounding the light pipes. The light pipes are aligned with the pixels of the pixel array. The invention also provides a method for fabricating the image sensing device. | 01-28-2016 |
20160033688 | DOUBLE-LENS STRUCTURES AND FABRICATION METHODS THEREOF - A double-lens structure and a method for fabricating the same are provided. The double-lens structure includes a first lens structure formed of a color filter layer having a first refractive index and a second lens structure formed of a micro-lens material layer having a second refractive index and disposed on the first lens structure. The first refractive index of the color filter layer is different from the second refractive index of the micro-lens material layer. An incident light enters the second lens structure and then passes through the first lens structure. Further, a method for fabricating the double-lens structure is also provided. | 02-04-2016 |
20160056193 | IMAGE SENSING DEVICE AND METHOD FOR FABRICATING THE SAME - An image sensing device includes: an active layer with a plurality of photo-sensing elements; a color pattern disposed over one of the photo-sensing elements, wherein the color pattern has a color selected from the group consisting of red (R), green (G), and blue (B); a microlens disposed on the color pattern; and a transmissive pattern being adjacent to the color pattern and over another one of the photo-sensing elements, wherein the transmissive pattern includes a color filter portion and a microlens portion, and an absolute value of a difference of refractive indexes between the microlens and the color pattern is less than 0.3, and there is no difference of refractive indexes between the microlens portion and the color filter portion of the transmissive pattern. | 02-25-2016 |
Patent application number | Description | Published |
20130210173 | Multiple Zone Temperature Control for CMP - To provide improved planarization, techniques in accordance with this disclosure include a CMP station that includes a plurality of concentric temperature control elements arranged over a number of concentric to-be-polished wafer surfaces. During polishing, a wafer surface planarity sensor monitors relative heights of the concentric to-be-polished wafer surfaces, and adjusts the temperatures of the concentric temperature control elements to provide an extremely well planarized wafer surface. Other systems and methods are also disclosed. | 08-15-2013 |
20130210323 | CMP Pad Cleaning Apparatus - The present disclosure relates to a two-phase cleaning element that enhances polishing pad cleaning so as to prevent wafer scratches and contamination in chemical mechanical polishing (CMP) processes. In some embodiments, the two-phase pad cleaning element comprises a first cleaning element and a second cleaning element configured to successively operate upon a section of a CMP polishing pad. The first cleaning element comprises a megasonic cleaning jet configured to utilize cavitation energy to dislodge particles embedded in the CMP polishing pad without damaging the surface of the polishing pad. The second cleaning element is configured to apply a high pressure mist, comprising two fluids, to remove by-products from the CMP polishing pad. By using megasonic cleaning to dislodge embedded particles a two-fluid mist to flush away by-products (e.g., including the dislodged embedded particles), the two-phase pad cleaning element enhances polishing pad cleaning. | 08-15-2013 |
20130217306 | CMP Groove Depth and Conditioning Disk Monitoring - Some embodiments relate to a chemical mechanical polishing (CMP) system. The CMP system includes a polishing pad having a polishing surface, and a wafer carrier to retain a wafer proximate to the polishing surface during polishing. A motor assembly rotates the polishing pad and concurrently rotates the wafer during polishing of the wafer. A conditioning disk has a conditioning surface that is in frictional engagement with the polishing surface during polishing. A torque measurement element measures a torque exerted by the motor assembly during polishing. A condition surface analyzer determines a surface condition of the conditioning surface or the polishing surface based on the measured torque. Other systems and methods are also disclosed. | 08-22-2013 |
20140196744 | METHOD AND DEVICE FOR CLEANING A BRUSH SURFACE HAVING A CONTAMINATION - A method for cleaning a brush surface having a contamination is provided. The method includes steps of: providing a mechanical wave; and stripping off the contamination from the brush surface by the mechanical wave. | 07-17-2014 |
20140220863 | HIGH THROUGHPUT CMP PLATFORM - A chemical-mechanical polishing system has a first polishing apparatus configured to perform a first chemical-mechanical polish on a workpiece and a second polishing apparatus configured to perform a second chemical-mechanical polish on the workpiece. A rework polishing apparatus comprising a rework platen and a rework CMP head is configured to perform an auxiliary chemical-mechanical polish on the workpiece when the workpiece is positioned on the rework platen. A measurement apparatus measures one or more parameters of the workpiece, and a transport apparatus transports the workpiece between the first polishing apparatus, second polishing apparatus, rework polishing apparatus, and measurement apparatus. A controller determines a selective transport of the workpiece to the rework polishing apparatus by the transport apparatus only when the one or more parameters are unsatisfactory. | 08-07-2014 |
20150352686 | CHEMICAL MECHANICAL POLISHING (CMP) PLATFORM FOR LOCAL PROFILE CONTROL - A localized chemical mechanical polishing (CMP) platform is provided. A table is configured to support a workpiece with a to-be-polished surface. A polishing pad is spaced from the table with a width less than about half that of the table. The polishing pad is configured to individually polish rough regions of hillocks or valleys on the to-be-polished surface. A slurry distribution system is configured to apply slurry to an interface between the polishing pad and the workpiece. A cleaning system is configured to clean the workpiece in situ on the table. A drying system is configured to dry the workpiece in situ on the table. A method for CMP with local profile control and a system with local profile control are also provided. | 12-10-2015 |
Patent application number | Description | Published |
20130228932 | Package on Package Structure - A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit. | 09-05-2013 |
20130270686 | METHODS AND APPARATUS FOR HEAT SPREADER ON SILICON - Apparatus and methods for forming a heat spreader on a substrate to release heat for a semi-conductor package are disclosed. The apparatus comprises a substrate. A dielectric layer is formed next to the substrate and in contact with a surface of the substrate. A heat spreader is formed next to the substrate and in contact with another surface of the substrate. A passivation layer is formed next to the dielectric layer. A connection pad is placed on top of the passivation layer. The substrate may comprise additional through-silicon-vias. The contact surface between the substrate and the heat spreader may be a scraggy surface. The packaging method further proceeds to connect a chip to the connection pad by way of a connection device such as a solder ball or a bump. | 10-17-2013 |
20130285237 | Low Profile Interposer with Stud Structure - An interposer includes a substrate having a contact pad structure and a stud operably coupled to the contact pad structure. A solder ball is seated on the contact pad structure and formed around the stud. The stud is configured to regulate a collapse of the solder ball when a top package is mounted to the substrate. | 10-31-2013 |
20140160688 | Methods and Apparatus for Package with Interposers - Methods and apparatus for an interposer with a dam used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure. | 06-12-2014 |
20140167263 | Methods and Apparatus for Package with Interposers - Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well. | 06-19-2014 |
20140264824 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface. | 09-18-2014 |
20140264849 | Package-on-Package Structure - A device comprises a bottom package mounted on a printed circuit board, wherein the bottom package comprises a plurality of first bumps formed between the bottom package and the printed circuit board, a first underfill layer formed between the printed circuit board and the bottom package, a semiconductor die mounted on the bottom package and a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps and the top package and the bottom package form a ladder shaped structure. The device further comprises a second underfill layer formed between the bottom package and the top package, wherein the second underfill layer is formed of a same material as the first underfill layer. | 09-18-2014 |
Patent application number | Description | Published |
20110291187 | Double Diffused Drain Metal-Oxide-Semiconductor Devices with Floating Poly Thereon and Methods of Manufacturing The Same - A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion. | 12-01-2011 |
20120241900 | SELF DETECTION DEVICE FOR HIGH VOLTAGE ESD PROTECTION - An electrostatic discharge (ESD) protected device may include a substrate, an N-type well region disposed corresponding to a first portion of the substrate and having two N+ segments disposed at a surface thereof, an a P-type well region disposed proximate to a second portion of the substrate and having a P+ segment and an N+ segment. The two N+ segments may be spaced apart from each other and each may each be associated with an anode of the device. The N+ segment may be associated with a cathode of the device. A contact may be positioned in a space between the two N+ segments and connected to the P+ segment. The contact may form a parasitic capacitance that, in connection with a parasitic resistance formed in association with the N+ segment, provides self detection for high voltage ESD protection. | 09-27-2012 |
20120292689 | Semiconductor Structure and Method for Operating the Same - A semiconductor structure and a method for operating the same are provided. The semiconductor structure includes a substrate, a first doped region, a second doped region, a third doped region, a first trench structure and a second gate structure. The first doped region is in the substrate. The first doped region has a first conductivity type. The second doped region is in the first doped region. The second doped region has a second conductivity type opposite to the first conductivity type. The third doped region having the first conductivity type is in the second doped region. The first trench structure has a first gate structure. The first gate structure and the second gate structure are respectively on different sides of the second doped region. | 11-22-2012 |
20130049067 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME AND ESD CIRCUIT - A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region. | 02-28-2013 |
20130056824 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device and a manufacturing method for the same are provided. The semiconductor device comprises a first doped region, a second doped region, a dielectric structure and a gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity and is adjacent to the first doped region. The dielectric structure comprises a first dielectric portion and a second dielectric portion separated from each other. The dielectric structure is formed on the first doped region. The gate structure is on a part of the first doped region or second doped region adjacent to the first dielectric portion. | 03-07-2013 |
20130249007 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a first source/drain region, a second source/drain region, a first stack structure and a second stack structure. The first source/drain region is formed in the substrate. The second source/drain region is formed in the substrate. The first stack structure is on the substrate between the first source/drain region and the second source/drain region. The first stack structure comprises a first dielectric layer and a first conductive layer on the first dielectric layer. The second stack structure is on the first stack structure. The second stack structure comprises a second dielectric layer and a second conductive layer on the second dielectric layer. | 09-26-2013 |
20140106532 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME AND ESD CIRCUIT - A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region. | 04-17-2014 |
20140197467 | HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE - A JFET structure includes a first JFET having a first terminal and a second JFET neighboring with the first JFET. Both JFETs commonly share the first terminal and the first terminal is between the gate of each JFET. The JFET also provides at least one tuning knob to adjust the pinch-off voltage and a tuning knob to adjust the breakdown voltage of the JFET structure. Moreover, the JFET has a buried layer as another tuning knob to adjust the pinch-off voltage of the JFET structure. | 07-17-2014 |
20140264581 | LOW ON RESISTANCE SEMICONDUCTOR DEVICE - A semiconductor device is provided having a dual dielectric layer structure defined by a thin dielectric layer adjacent to a thick dielectric layer. More particularly, a high voltage metal oxide semiconductor transistor having a dual gate oxide layer structure comprising a thin gate oxide layer adjacent to a thick oxide/thin oxide layer may be provided. Such structures may be used in extended drain metal oxide semiconductor field effect transmitters, laterally diffused metal oxide field effect transistors, or any high voltage metal oxide semiconductor transistor. Methods of fabricating an extended drain metal oxide semiconductor transistor device are also provided. | 09-18-2014 |
20150097236 | Semiconductor Device And Method Of Fabricating Same - A lateral drain metal oxide semiconductor (LDMOS) device includes a well region having a second conductive type in a substrate, a body region having a first conductive type in the well region, a drift region having the second conductive type in the well region and spaced apart from the body region, a source region having the second conductive type in the body region, a drain region having the second conductive type in the drift region, a gate structure on the well region between the source region and the drain region, a shallow trench isolation (STI) structure in the drift region between the drain region and the source region, and a buried layer having the first conductive type in the well region under the drift region, a center of the buried layer being aligned with a center of the STI structure. | 04-09-2015 |
20160027773 | SEMICONDUCTOR DEVICE - A semiconductor device includes high-voltage (HV) and low-voltage (LV) MOS's formed in a substrate. The HV MOS includes a first semiconductor region having a first-type conductivity and a first doping level, a second semiconductor region having the first-type conductivity and a second doping level lower than the first doping level, a third semiconductor region having a second-type conductivity, and a fourth semiconductor region having the first-type conductivity. The first, second, third, and fourth semiconductor regions are arranged along a first direction, and are drain, drift, channel, and source regions, respectively, of the HV MOS. The LV MOS includes the fourth semiconductor region, a fifth semiconductor region having the second-type conductivity, and a sixth semiconductor region having the first-type conductivity. The fourth, fifth, and sixth semiconductor regions are arranged along a second direction different from the first direction, and are drain, channel, and source regions, respectively, of the LV MOS. | 01-28-2016 |
20160087083 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - A lateral drain metal oxide semiconductor (LDMOS) device includes a well region having a second conductive type in a substrate, a body region having a first conductive type in the well region, a drift region having the second conductive type in the well region and spaced apart from the body region, a source region having the second conductive type in the body region, a drain region having the second conductive type in the drift region, a gate structure on the well region between the source region and the drain region, a shallow trench isolation (STI) structure in the drift region between the drain region and the source region, and a buried layer having the first conductive type in the well region under the drift region, a center of the buried layer being aligned with a center of the STI structure | 03-24-2016 |
Patent application number | Description | Published |
20090039424 | HIGH-VOLTAGE MOS TRANSISTOR DEVICE - A high-voltage transistor device has a substrate, an isolation structure, a source, a gate, a drain, a plurality of doped regions, a plurality of ion wells, and a first dielectric layer disposed on the substrate. The high-voltage transistor device further has a first conductive layer and a plurality of first field plate rings. The first conductive layer is electrically connected to the drain and at least one of the first field plate rings. | 02-12-2009 |
20110080213 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first gate. The junction field effect transistor includes a second source, the common drain and a second gate. The second source is electrically connected to the first gate. The inner circuit is electrically connected to the first source. | 04-07-2011 |
20120038414 | METHOD FOR OPERATING SEMICONDUCTOR DEVICE - A method for operating a semiconductor device including a lateral double diffused metal oxide semiconductor (LDMOS) with a first source, a common drain and a first gate, a junction field effect transistor (JFET) with a second source, the common drain and a second gate wherein the second source is electrically connected to the first gate and an inner circuit electrically connected to the first source is provided. The first source provides the inner circuit with an inner current to generate an inner voltage by means of the lateral double diffused metal oxide semiconductor, and the lateral double diffused metal oxide semiconductor turns off when the inner voltage is elevated substantially as high as the first gate voltage. | 02-16-2012 |