Patent application number | Description | Published |
20090320688 | Laminar Scrubber Apparatus for Capturing Carbon Dioxide From Air and Methods of Use - The present invention is directed to methods for carbon dioxide from air, which comprises exposing solvent covered surfaces to air streams where the airflow is kept laminar, or close to the laminar regime. The invention also provides for an apparatus, which is a laminar scrubber, comprising solvent covered surfaces situated such that they can be exposed to air streams such that the airflow is kept laminar. | 12-31-2009 |
20110056382 | LAMINAR SCRUBBER APPARATUS FOR CAPTURING CARBON DIOXIDE FROM AIR AND METHODS OF USE - The present invention is directed to methods for carbon dioxide from air, which comprises exposing solvent covered surfaces to air streams where the airflow is kept laminar, or close to the laminar regime. The invention also provides for an apparatus, which is a laminar scrubber, comprising solvent covered surfaces situated such that they can be exposed to air streams such that the airflow is kept laminar. | 03-10-2011 |
20110108421 | ELECTROCHEMICAL METHODS AND PROCESSES FOR CARBON DIOXIDE RECOVERY FROM ALKALINE SOLVENTS FOR CARBON DIOXIDE CAPTURE FROM AIR - The present invention relates to methods for recovering a hydroxide based sorbent from carbonate or another salt by electrochemical means involving separation schemes that use bipolar membranes and at least one type of cationic or anionic membrane. The methods can be used in an air contactor that removes carbon dioxide from the air by binding the carbon dioxide into a solvent or sorbent. | 05-12-2011 |
20140219899 | Methods and Systems for Capturing Carbon Dioxide From Dilute Sources - Methods and systems for capturing carbon dioxide from dilute sources are disclosed. In some embodiments, the methods include the following: (a) directing a first substantially gaseous stream including a first amount of carbon dioxide to a primary scrubber; (b) in the primary scrubber, removing a portion of the first amount of carbon dioxide thereby forming a second substantially gaseous stream including a second amount of carbon dioxide; (c) directing the second substantially gaseous stream to a secondary scrubber; (d) in the secondary scrubber, removing a portion of the second amount of carbon dioxide thereby forming a third substantially gaseous stream; (e) mixing substantially all of the portion of the second amount of carbon dioxide removed in step (d) with the first substantially gaseous stream before it enters the primary scrubber; and (f) repeating steps (a) thru (e). | 08-07-2014 |
Patent application number | Description | Published |
20100279467 | METHODOLOGY FOR PROCESSING A PANEL DURING SEMICONDUCTOR DEVICE FABRICATION | 11-04-2010 |
20120021565 | METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE - A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface. | 01-26-2012 |
20130049217 | SEMICONDUCTOR DEVICE PACKAGING HAVING PRE-ENCAPSULATION THROUGH VIA FORMATION USING DROP-IN SIGNAL CONDUITS - A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications. | 02-28-2013 |
20130078753 | CAPPED DEVICE INTERCONNECT IN A SEMICONDUCTOR PACKAGE - A method for fabricating a thin package that encapsulates a capped MEMS device electrically coupled with one or more encapsulated semiconductor devices is provided. A wafer-level packaging methodology is used in which the capped MEMS device is electrically coupled to a package interconnect, which then allows for electrical coupling to the one or more encapsulated semiconductor devices, as well as external connections. | 03-28-2013 |
20130154091 | SEMICONDUCTOR DEVICE PACKAGING USING ENCAPSULATED CONDUCTIVE BALLS FOR PACKAGE-ON-PACKAGE BACK SIDE COUPLING - A semiconductor device package having an embedded three-dimensional interconnect structure and a process for making such a package is provided. One or more ball conductors are attached to a major surface of a substrate that provides at least an electrical conduit from the ball conductor to an opposite major surface of the substrate. The substrate can also provide an interconnect between solder balls. The combination of solder balls and substrate is encapsulated in the semiconductor device package. The ends of the signal conduits are exposed on one major surface of the device package, while a portion of the ball conductors is exposed on the opposite major surface of the device package. The ball conductors and signal conduits provide signal-bearing pathways between the major surfaces of the package. Contacts created by the back grinded ball conductors are used to form a package-on-package structure by coupling with contacts from another package. | 06-20-2013 |
20140054783 | STACKED MICROELECTRONIC PACKAGES HAVING SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF - Methods for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging a plurality of microelectronic device panels in a panel stack. Each microelectronic device panel contains plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are created in the panel stack exposing the plurality of package edge conductors, and a plurality of sidewall conductors is formed interconnecting different ones of the package edge conductors exposed through the trenches. The panel stack is then separated into a plurality of stacked microelectronic packages each including at least two microelectronic devices electrically interconnected by at least one of the plurality of sidewall conductors included within the stacked microelectronic package. | 02-27-2014 |
20140054796 | STACKED MICROELECTRONIC PACKAGES HAVING PATTERENED SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF - Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package. | 02-27-2014 |
20140054797 | STACKED MICROELECTRONIC PACKAGES HAVING SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF - Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors. | 02-27-2014 |
20140264945 | STACKED MICROELECTRONIC PACKAGES HAVING SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF - A stacked microelectronic package can comprise a package body having an external vertical package sidewall, a plurality of microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the external vertical package sidewall. A cavity is formed on an external surface of the package body between a first one of the package edge conductors and a second one of the package edge conductors. Electrically conductive material is in the cavity and in electrical contact with a first and a second one of the package edge conductors, wherein the conductive material in the cavity is within planform dimensions of the microelectronic package. | 09-18-2014 |
20150092377 | DEVICES AND STACKED MICROELECTRONIC PACKAGES WITH IN-TRENCH PACKAGE SURFACE CONDUCTORS AND METHODS OF THEIR FABRICATION - Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body between exposed ends of first and second device-to-edge conductors, and forming a package surface conductor in the trench to electrically couple the first and second device-to-edge conductors. In one embodiment, the package surface conductor is formed by first forming a conductive material layer over the package surface, where the conductive material layer substantially fills the trench, and subsequently removing portions of the conductive material layer from the package surface adjacent to the trench. In another embodiment, the package surface conductor is formed by dispensing one or more conductive materials in the trench between the first and second exposed ends (e.g., using a technique such as spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispense). Excess conductive material may then be removed from the package surface adjacent to the trench. | 04-02-2015 |
20150115454 | MICROELECTRONIC PACKAGES HAVING LAYERED INTERCONNECT STRUCTURES AND METHODS FOR THE MANUFACTURE THEREOF - Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure. | 04-30-2015 |
20150162310 | DEVICES AND STACKED MICROELECTRONIC PACKAGES WITH PACKAGE SURFACE CONDUCTORS AND ADJACENT TRENCHES AND METHODS OF THEIR FABRICATION - Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body in an area adjacent to where first and second package surface conductors will be (or have been) formed on both sides of the trench. The method also includes forming the first and second package surface conductors to electrically couple exposed ends of various combinations of device-to-edge conductors. The trench may be formed using laser cutting, drilling, sawing, etching, or another suitable technique. The package surface conductors may be formed by dispensing (e.g., coating, spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispensing) one or more conductive materials on the package body surface between the exposed ends of the device-to-edge conductors. | 06-11-2015 |
20150243635 | STACKED MICROELECTRONIC PACKAGES HAVING SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF - Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors. | 08-27-2015 |
20150262931 | MICROELECTRONIC PACKAGES HAVING MOLD-EMBEDDED TRACES AND METHODS FOR THE PRODUCTION THEREOF - Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace. | 09-17-2015 |
20150270233 | WAFER LEVEL PACKAGES AND METHODS FOR PRODUCING WAFER LEVEL PACKAGES HAVING DELAMINATION-RESISTANT REDISTRIBUTION LAYERS - Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer. | 09-24-2015 |
Patent application number | Description | Published |
20110284742 | DETECTION OF Kr-85 GAMMA RAYS FOR POSITIVE VERIFICATION OF MASS IN PRESSURIZED BOTTLES - A Kr-85 tracer gas is mixed with the carrier gas in a pressurized bottle. External detection of the gamma rays that penetrate through the walls of the bottle provides a non-invasive technique for the positive verification of mass inside the bottle over the lifetime of the bottle | 11-24-2011 |
20120068018 | ORBITAL DEBRIS MITIGATION SYSTEM AND METHOD - Fiber-based debris interceptors are used to intercept and/or contain space debris. The debris interceptors may be made up of fibers that are formed in space from a material supply on a space vehicle. The fibers for the debris interceptors may be formed by extrusion, with a heat source, such as a mirror to focus sunlight, used to heat the material of the material supply that is carried on the space vehicle. The debris interceptor may be separated from the space vehicle, and used to remove debris from an orbit, or otherwise prevent debris entering an orbit from damaging a satellite or other spacecraft that travels in that orbit. The debris interceptor may be deployed prior to later launch of a valuable spacecraft, in order to “cleanse” the intended orbit of debris. Debris objects may pass through the debris interceptor, but in so doing may lose energy so as to de-orbit. | 03-22-2012 |
20120104148 | GUIDED MUNITIONS INCLUDING SELF-DEPLOYING DOME COVERS AND METHODS FOR EQUIPPING GUIDED MUNITIONS WITH THE SAME - Embodiments of a guided munition are provided, as are embodiments of a method for equipping a guided munition with a self-deploying dome cover. In one embodiment, the guided munition includes a munition body, a seeker dome coupled to the munition body, and a self-deploying dome cover disposed over the seeker dome. The self-deploying dome cover is configured to deploy and expose the seeker dome during munition flight in response to aerodynamic forces acting on the self-deploying dome cover. | 05-03-2012 |
20120104149 | GUIDED MUNITION SYSTEMS INCLUDING COMBUSTIVE DOME COVERS AND METHODS FOR EQUIPPING GUIDED MUNITIONS WITH THE SAME - Embodiments of a guided munition system are provided, as are embodiments of a combustive dome cover and methods for equipping a guided munition with a combustive dome cover. In one embodiment, the guided munition system includes a guided munition, which has a munition body and a seeker dome coupled thereto, and a combustive dome cover disposed over the seeker dome. The combustive dome cover is configured to uncover the seeker dome at a predetermined time of deployment and to combust when so deployed to minimize the production of debris. | 05-03-2012 |
20140118514 | METHOD AND APPARATUS FOR IMAGE STACKING - An optical imaging system and method in which a second channel is used to provide alignment data for achieving image frame stacking of image data in a first channel. In one example, image stacking of infrared images is achieved by obtaining and analyzing corresponding visible images to provide alignment data that is then used to align and stack the infrared images. | 05-01-2014 |
20150028212 | DUAL FIELD OF VIEW TELESCOPE - A multiple field-of-view telescope and optical sensor system and imaging methods using the system. In one example, an optical sensor system includes a primary imaging detector having a first field of view, a telescope configured to receive and focus electromagnetic radiation onto the primary imaging detector along a primary optical axis, a secondary detector having a second field of view different from the first field of view, and relay optics configured to direct and focus a portion of the electromagnetic radiation onto the secondary detector. In certain examples, the system further includes a fold mirror positioned to reflect the portion of the electromagnetic radiation to the relay optics. | 01-29-2015 |
Patent application number | Description | Published |
20130132664 | PERIODIC DESTAGES FROM INSIDE AND OUTSIDE DIAMETERS OF DISKS TO IMPROVE READ RESPONSE TIMES - A storage controller that includes a cache, receives a command from a host, wherein a set of criteria corresponding to read response times for executing the command have to be satisfied. A destage application that destages tracks based at least on recency of usage and spatial location of the tracks is executed, wherein a spatial ordering of the tracks is maintained in a data structure, and the destage application traverses the spatial ordering of the tracks. Tracks are destaged from at least inside or outside diameters of disks at periodic intervals, while traversing the spatial ordering of the tracks, wherein the set of criteria corresponding to the read response times for executing the command are satisfied. | 05-23-2013 |
20130132667 | ADJUSTMENT OF DESTAGE RATE BASED ON READ AND WRITE RESPONSE TIME REQUIREMENTS - A storage controller that includes a cache receives a command from a host, wherein a set of criteria corresponding to read and write response times for executing the command have to be satisfied. The storage controller determines ranks of a first type and ranks of a second type corresponding to a plurality of volumes coupled to the storage controller, wherein the command is to be executed with respect to the ranks of the first type. Destage rate corresponding to the ranks of the first type are adjusted to be less than a default destage rate corresponding to the ranks of the second type, wherein the set of criteria corresponding to the read and write response times for executing the command are satisfied. | 05-23-2013 |
20130191596 | ADJUSTMENT OF DESTAGE RATE BASED ON READ AND WRITE RESPONSE TIME REQUIREMENTS - A storage controller that includes a cache receives a command from a host, wherein a set of criteria corresponding to read and write response times for executing the command have to be satisfied. The storage controller determines ranks of a first type and ranks of a second type corresponding to a plurality of volumes coupled to the storage controller, wherein the command is to be executed with respect to the ranks of the first type. Destage rate corresponding to the ranks of the first type are adjusted to be less than a default destage rate corresponding to the ranks of the second type, wherein the set of criteria corresponding to the read and write response times for executing the command are satisfied. | 07-25-2013 |
20130235709 | PERIODIC DESTAGES FROM INSIDE AND OUTSIDE DIAMETERS OF DISKS TO IMPROVE READ RESPONSE TIMES - A storage controller that includes a cache, receives a command from a host, wherein a set of criteria corresponding to read response times for executing the command have to be satisfied. A destage application that destages tracks based at least on recency of usage and spatial location of the tracks is executed, wherein a spatial ordering of the tracks is maintained in a data structure, and the destage application traverses the spatial ordering of the tracks. Tracks are destaged from at least inside or outside diameters of disks at periodic intervals, while traversing the spatial ordering of the tracks, wherein the set of criteria corresponding to the read response times for executing the command are satisfied. | 09-12-2013 |