Patent application number | Description | Published |
20090083471 | METHOD AND APPARATUS FOR PROVIDING ACCELERATOR SUPPORT IN A BUS PROTOCOL - The present invention provides a method and apparatus for processing a bus protocol packet in order to provide accelerator support. A component receives a bus protocol packet having a requester identifier. The component looks up an agent routing field. The component routes the bus protocol packet to an accelerator agent based on the agent routing field. It processes the bus protocol packet at the accelerator agent based on the agent routing field. | 03-26-2009 |
20090144452 | IMPLEMENTING CONDITIONAL PACKET ALTERATIONS BASED ON TRANSMIT PORT - A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array. | 06-04-2009 |
20090150642 | Indexing Page Attributes - Embodiments of the invention provide methods and apparatus for increasing the number of page attributes specified by a page table while minimizing an increase in size of the page table. According to embodiments of the invention, attribute index bits may be included within a page table and may be used to determine page attributes stored within an attribute index. Additionally, embodiments of the invention provide a plurality of new page attributes. | 06-11-2009 |
20110029738 | LOW-COST CACHE COHERENCY FOR ACCELERATORS - Embodiments of the invention provide methods and systems for reducing the consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs. The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing environment. Each node that contains a shared memory device may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, commands and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, the inter-chip bandwidth consumed for maintaining coherence may be reduced. | 02-03-2011 |
20120173842 | Operating System Management of Address-Translation-Related Data Structures and Hardware Lookasides - An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled. | 07-05-2012 |
20120284465 | Operating System Management of Address-Translation-Related Data Structures and Hardware Lookasides - An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled. | 11-08-2012 |