Patent application number | Description | Published |
20100103572 | AMPLIFIER WITH IMPROVED ESD PROTECTION CIRCUITRY - An amplifier (e.g., an LNA) with improved ESD protection circuitry is described. In one exemplary design, the amplifier includes a transistor, an inductor, and a clamp circuit. The transistor has a gate coupled to a pad and provides signal amplification for the amplifier. The inductor is coupled to a source of the transistor and provides source degeneration for the transistor. The clamp circuit is coupled between the gate and source of the transistor and provides ESD protection for the transistor. The clamp circuit may include at least one diode coupled between the gate and source of the transistor. The clamp circuit conducts current through the inductor to generate a voltage drop across the inductor when a large voltage pulse is applied to the pad. The gate-to-source voltage (Vgs) of the transistor is reduced by the voltage drop across the inductor, which may improve the reliability of the transistor. | 04-29-2010 |
20100225347 | Circuit for Measuring Magnitude of Electrostatic Discharge (ESD) Events for Semiconductor Chip Bonding - A circuit for recording a magnitude of an ESD event during semiconductor assembly includes a voltage divider connected between an input and a ground. The circuit also includes a measurement block having a recorder device. Each measurement block receives current from a segment of the voltage divider. The magnitude of the ESD event is determined based upon a read-out of the measurement devices after the ESD event. The recorder device may be a capacitor that would be damaged during the ESD event. During the ESD event the capacitor may be damaged. Reading out the recorder device determines if the magnitude of the ESD event exceeded a threshold magnitude that damages the capacitor. | 09-09-2010 |
20100232077 | GATED DIODE HAVING AT LEAST ONE LIGHTLY-DOPED DRAIN (LDD) IMPLANT BLOCKED AND CIRCUITS AND METHODS EMPLOYING SAME - Gated diodes, manufacturing methods, and related circuits are provided wherein at least one lightly-doped drain (LDD) implant is blocked in the gated diode to reduce its capacitance. In this manner, the gated diode may be used in circuits and other applications whose performance is sensitive to load capacitance while still obtaining the performance characteristics of a gated diode. These characteristics include fast turn-on times and high conductance, making the gated diodes disclosed herein well-suited for electro-static discharge (ESD) protection circuits as one application example. The examples of the gated diode disclosed herein include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region, wherein a P-N junction is formed. At least one LDD implant is blocked in the gated diode to reduce capacitance. | 09-16-2010 |
20100321841 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - Disclosed herein are embodiments of electrostatic discharge (ESD) protection circuits. In certain embodiments an ESD protection circuit may include two series resistor-capacitor (RC) circuits. One series RC circuit may have a short time constant and may selectively activate a current shunt between two power rails in response to an ESD event. Accordingly, the ESD circuit may be able to respond to fast ramping ESD events. The other series RC circuit has a longer time constant, and maintains the current shunt in an active state for a sufficient amount of time to allow the ESD event to be completely discharged. | 12-23-2010 |
20110084362 | Active Diode Having No Gate and No Shallow Trench Isolation - An active diode with fast turn-on time, low capacitance, and low turn-on resistance may be manufactured without a gate and without a shallow trench isolation region between doped regions of the diode. A short conduction path in the active diode allows a fast turn-on time, and a lack of gate oxide reduces susceptibility of the active diode to extreme voltages. The active diode may be implemented in integrated circuits to prevent and reduce damage from electrostatic discharge (ESD) events. Manufacturing the active diode is accomplished by depositing a salicide block between doped regions of the diode before salicidation. After the salicide layers are formed on the doped regions, the salicide block is removed. | 04-14-2011 |
20110176245 | HIGH VOLTAGE, HIGH FREQUENCY ESD PROTECTION CIRCUIT FOR RF ICs - Improved ESD protection circuits for RFICs requiring both high voltage and high frequency operation is described. A cascode grounded gate snap-back NFET (GGNFET) combined with a precharge circuit and a diode network results in a positive ESD protection clamp with low capacitance and high turn-on voltage. The positive ESD protection clamp provides ESD protection to an IC during a positive voltage ESD pulse. Exemplary embodiments of a negative ESD protection clamp are disclosed where a bias circuit or a charge pump is used in place of the precharge circuit in a manner that allows the combination of the bias circuit or the charge pump together with a diode network and a cascode grounded gate snap-back NFET to provide protection against negative ESD voltage pulses. The combination of a positive and a negative ESD protection clamp provides ESD protection to an IC during either a positive or a negative voltage ESD pulse. Alternate embodiments further reduce the capacitance of the ESD protection circuit by using only a positive ESD clamp to provide ESD protection during a positive ESD pulse while protection for a negative ESD pulse is provided by a discharge path formed by a path of an RF front-end switch coupled to a negative ESD diode. | 07-21-2011 |
20120236444 | CHARGE PUMP ELECTROSTATIC DISCHARGE PROTECTION - Techniques for electrostatic discharge (ESD) protection for amplifiers and other circuitry employing charge pumps. In an exemplary embodiment, a Vneg switch coupling a second flying capacitor node to a negative output voltage node is closed in response to an ESD event being detected between a supply voltage node and the negative output voltage node. A ground switch coupling a ground node to the second flying capacitor node is closed in response to an ESD event being detected between the ground node and the negative output voltage node. The Vneg switch is further closed in response to the ESD event being detected between the ground node and the negative output voltage node. Further techniques are disclosed for providing on-chip snapback clamps at the output of a power amplifier coupled to the charge pump to protect against ESD events as defined by the standard IEC 61000-4-2. | 09-20-2012 |
20140098447 | ELECTROSTATIC DISCHARGE PROTECTION FOR CLASS D POWER AMPLIFIERS - Electrostatic discharge protection for Class D power amplifiers is disclosed. In an exemplary embodiment, an apparatus includes an amplifier having an output transistor coupled to an interface pad, a snapback supply clamp coupled across first and second supplies of the amplifier and configured to provide a clamp voltage across the first and second supplies during ESD event; and a trigger circuit coupled to the output transistor, the trigger circuit configured to detect the clamp voltage and to enable the output transistor to provide a discharge path from the interface pad to the second supply when the clamp voltage is detected. | 04-10-2014 |
20140204488 | ESD CLAMPING TRANSISTOR WITH SWITCHABLE CLAMPING MODES OF OPERATION - In a particular embodiment, an apparatus includes an electrostatic discharge (ESD) clamping transistor coupled to a ground terminal of a device. The apparatus further includes a switch coupled between a body terminal of the ESD clamping transistor and the around terminal. | 07-24-2014 |
Patent application number | Description | Published |
20090121236 | Optocoupler using silicon based LEDs - This invention details how a low cost opto coupler can be made on Silicon On Insulator (SOI) using conventional integrated circuit processing methods. Specifically, metal and deposited insulating materials are use to realize a top reflector for directing light generated by a silicon PN junction diode to a silicon PN junction photo diode detector. The light generator or LED can be operated either in the avalanche mode or in the forward mode. Also, side reflectors are described as a means to contain the light to the LED-photo detector pair. Furthermore, a serpentine junction PN silicon LED is described for the avalanche mode of the silicon LED. For the forward mode, two LED structures are described in which hole and electrons combine in lightly doped regions away from heavily doped regions thereby increasing the LED conversion efficiency. | 05-14-2009 |
20100128511 | High density prom - The invention shows how diodes in a modern semiconductor process can be used as a very compact switch element in a Programmable Read Only Memory (PROM) using common integrated circuit fuse elements such as polysilicon and metal. This compact switch element allows very dense PROM arrays to be realized since diodes have the highest conduction density of any semiconductor device. The high conduction density is used to provide the relatively high current needed to blow the fuse element open. Since MOSFETs are typically used as fuse array switch elements, a relatively large area is required for the MOSFET to reach the current needed to blow the fuse element. Since diodes are two terminal switch elements unlike MOSFETs which are three terminal devices, methods are outlined on how to both read and write the arrays using this two terminal switch. | 05-27-2010 |
20140198414 | ELECTROSTATIC DISCHARGE CLAMP WITH DISABLE - In a particular embodiment, a circuit includes a power supply, a ground, and a clamping transistor circuit coupled to the power supply and to the ground. The circuit further includes a disable clamp circuit. The disable clamp circuit is coupled to the power supply and is responsive to a second power supply input to selectively disable the clamping transistor circuit by modifying a charging current applied to a capacitor of the clamping transistor circuit. In a particular embodiment, modifying the charging current includes enabling a second charging path. Enabling the second charging path enables charging the capacitor at a higher charging rate than a charging rate associated with charging the capacitor via a first charging path. | 07-17-2014 |
20140254051 | DEVICES AND METHODS FOR CALIBRATING AND OPERATING A SNAPBACK CLAMP CIRCUIT - A device includes a snapback clamp circuit configured to clamp a supply voltage in response to the supply voltage exceeding a trigger voltage level. In at least one embodiment, the snapback clamp circuit includes a clamp transistor and a programmable resistance portion that is responsive to a control signal to calibrate the trigger voltage level. Alternatively or in addition, the snapback clamp circuit may include a programmable bias device configured to calibrate the trigger voltage level by biasing a gate terminal of the clamp transistor. In another particular embodiment, a method of calibrating a snapback clamp circuit is disclosed. In another particular embodiment, a method of operating an integrated circuit is disclosed. | 09-11-2014 |
20140268446 | RADIO FREQUENCY INTEGRATED CIRCUIT (RFIC) CHARGED-DEVICE MODEL (CDM) PROTECTION - An apparatus is described. The apparatus includes an input device. The apparatus also includes a positive supply voltage pad. The apparatus further includes an input signal pad. The apparatus also includes a ground pad. The apparatus further includes charged-device model protection circuitry that protects the input device from electrostatic discharge. The charged-device model protection circuitry includes at least one of de-Q circuitry and a cascode device. | 09-18-2014 |
20140268447 | RADIO FREQUENCY INTEGRATED CIRCUIT (RFIC) CHARGED-DEVICE MODEL (CDM) PROTECTION - An apparatus is described. The apparatus includes an input device. The apparatus also includes a positive supply voltage pad. The apparatus further includes an input signal pad. The apparatus also includes a ground pad. The apparatus further includes charged-device model protection circuitry that protects the input device from electrostatic discharge. The charged-device model protection circuitry includes at least one of de-Q circuitry and a cascode device. | 09-18-2014 |
20150084161 | MIXED MODE RC CLAMPS - A system interconnect includes a first resistor-capacitor (RC) clamp having a first RC time constant. The system interconnect also includes second RC clamps having a second RC time constant. The first and second RC clamps are arranged along the system interconnect. In addition, the first RC time constant is different from the second RC time constant. | 03-26-2015 |
20150249334 | ELECTROSTATIC DISCHARGE CIRCUIT WITH REDUCED STANDBY CURRENT - Techniques for reducing leakage current during normal operation of an electrostatic discharge (ESD) circuit are described herein. In one embodiment, a circuit comprises an internal circuit and an electrostatic discharge (ESD) rail clamp coupled in parallel to the internal circuit and between first and second power supply rails. The ESD rail clamp is operable to shunt ESD current from the first power supply rail to the second power supply rail via a low resistance shunt path. The ESD rail clamp comprises an ESD trigger circuit configured to detect an ESD event and a plurality of discharging transistors coupled in series. The ESD trigger circuit is configured to turn off the discharging transistors during normal operation and to turn on the discharging transistors to form the low resistance shunt path in response to detection of the ESD event. | 09-03-2015 |
Patent application number | Description | Published |
20080225030 | Display with multiplexed pixels and driving methods - A multiplexed pixel display includes a plurality of pixel electrodes, a plurality of storage elements, a first voltage supply terminal, a second voltage supply terminal, a common electrode, and a plurality of multiplexers each selectively coupling an associated one of the pixel electrodes with one of the first voltage supply terminal and the second voltage supply terminal responsive to a value of a data bit stored in an associated one of said storage elements. A controller is configured to sequentially write each bit of multi-bit data words to the storage elements, and assert, while each bit is stored in the storage elements, a first predetermined voltage on the first voltage supply terminal, a second predetermined voltage on the second voltage supply terminal, and a third predetermined voltage on the common electrode, for a time dependent on the significance of the stored bit. Various alternate controllers facilitate the use of additional driving schemes. | 09-18-2008 |
20080248613 | Method of Forming a Micromechanical Device with Microfluidic Lubricant Channel - A micromechanical device assembly includes a micromechanical device enclosed within a processing region and a lubricant channel formed through an interior wall of the processing region and in fluid communication with the processing region. Lubricant is injected into the lubricant channel via capillary forces and held therein via surface tension of the lubricant against the internal surfaces of the lubrication channel. The lubricant channel containing the lubricant provides a ready supply of fresh lubricant to prevent stiction from occurring between interacting components of the micromechanical device disposed within the processing region. | 10-09-2008 |
20110215430 | MICROMECHANICAL DEVICE WITH MICROFLUIDIC LUBRICANT CHANNEL - A micromechanical device assembly includes a micromechanical device enclosed within a processing region and a lubricant channel formed through an interior wall of the processing region and in fluid communication with the processing region. Lubricant is injected into the lubricant channel via capillary forces and held therein via surface tension of the lubricant against the internal surfaces of the lubrication channel. The lubricant channel containing the lubricant provides a ready supply of fresh lubricant to prevent stiction from occurring between interacting components of the micromechanical device disposed within the processing region. | 09-08-2011 |