Patent application number | Description | Published |
20110037521 | POWER AMPLIFIER HAVING DEPLETION MODE HIGH ELECTRON MOBILITY TRANSISTOR - Provided is a power amplifier including: a depletion mode high electron mobility transistor (D-mode HEMT) configured to amplify a signal inputted to a gate terminal and output the amplified signal through a drain terminal; an input matching circuit configured to serially ground the gate terminal; and a DC bias circuit connected between the drain terminal and a ground. Through the foregoing configuration, the HEMT may be biased only by a single DC bias circuit without any biasing means to provide a negative voltage. Also, superior matching characteristic may be provided in various operation frequency bands through a shunt inductor and a choke inductor. | 02-17-2011 |
20110049698 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal. | 03-03-2011 |
20110057237 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THEREOF - Provided is a semiconductor device. The semiconductor device includes: a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; and a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall. | 03-10-2011 |
20110143505 | METHOD FOR FABRICATING FIELD EFFECT TRANSISTOR - Provided is a method for fabricating a field effect transistor. In the method, an active layer and a capping layer are formed on a substrate. A source electrode and a drain electrode is formed on the capping layer. A dielectric interlayer is formed on the substrate, and resist layers having first and second openings with asymmetrical depths are formed on the dielectric interlayer between the source electrode and the drain electrode. The first opening exposes the dielectric interlayer, and the second opening exposes the lowermost of the resist layers. The dielectric interlayer in the bottom of the first opening and the lowermost resist layer under the second opening are simultaneously removed to expose the capping layer to the first opening and expose the dielectric interlayer to the second opening. The capping layer of the first opening is removed to expose the active layer. A metal layer is deposited on the substrate to simultaneously form a gate electrode and a field plate in the first opening and the second opening. The resist layers are removed to lift off the metal layer on the resist layers. | 06-16-2011 |
20120086118 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor package and a method of fabricating the same. The semiconductor package includes: a package body including a plurality of sheets; semiconductor chips mounted in the package body; and an external connection terminal provided on a first side of the package body, wherein the sheets are stacked in a parallel direction to the first side. | 04-12-2012 |
20130040428 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal. | 02-14-2013 |
20130244379 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor package and a method of fabricating the same. The semiconductor package includes: a package body including a plurality of sheets; semiconductor chips mounted in the package body; and an external connection terminal provided on a first side of the package body, wherein the sheets are stacked in a parallel direction to the first side. | 09-19-2013 |
20140149099 | METHOD OF CONFIGURING LARGE SIGNAL MODEL OF ACTIVE DEVICE - Provided is a method of configuring a large signal model of an active device. The method may include configuring a large signal model of a first active device, preparing a first measured value on a first characteristic of a second active device, the second active device being larger than the first active device, processing the large signal model of the first active device using a circuit simulator to configure a large signal model of the second active device, simulating the large signal model of the second active device to obtain a calculated value on the first characteristic, comparing the measured and calculated values on the first characteristic to each other, and establishing the large signal model of the second active device, if a difference between the measured and calculated values on the first characteristic may be smaller than a predetermined error margin. Further, if the difference between the measured and calculated values on the first characteristic may be greater than the predetermined error margin, the large signal model of the second active device may be configured by modifying parameters of passive devices. | 05-29-2014 |
20140159115 | TRANSISTOR AND METHOD OF FABRICATING THE SAME - A high electron mobility transistor includes a T-type gate electrode disposed on a substrate between source and drain electrodes and insulating layers disposed between the substrate and the T-type gate electrode. The insulating layers include first, second, and third insulating layers. The third insulating layer is disposed between the substrate and a head portion of the T-type gate electrode such that a portion of the third insulating layer is in contact with a foot portion of the T-type gate electrode. The second insulating layer is disposed between the substrate and the head portion of the T-type gate electrode to be in contact with the third insulating layer. The first insulating layer and another portion of the third insulating layer are sequentially stacked between the substrate and the head portion of the T-type gate electrode to be in contact with the second insulating layer. | 06-12-2014 |