Patent application number | Description | Published |
20120135496 | Protein Belonging to the TNF Superfamily Involved in Signal Transduction, Nucleic Acids Encoding Same and Methods of Use Thereof - A method of modulating immune response in an animal is disclosed. Such a method interacting the immature dendritic cells from the animal with an antigen ex vivo so that the immature dendritic cells present the antigen on their surfaces, inducing maturation of the immature dendritic cells ex vivo, and contacting the mature dendritic cells ex vivo with a modulator comprising TRANCE, conservative variants thereof, fragments thereof, analogs or derivatives thereof, or a fusion protein comprising the amino acid sequence of TRANCE, conservative variants thereof, or fragments thereof. After contacting the modulator ex vivo, the mature dendritic cells are introduced into the animal. As a result, immune response in the animal towards the antigen is modulated relative to the immune response against the antigen in an animal in which dendritic cells did not interact with the antigen ex vivo, and did not contact a modulator ex vivo. Preferably, the method of the present invention results in increasing immune response towards the antigen in the animal. | 05-31-2012 |
20130064813 | Protein Belonging to the TNF Superfamily Involved in Signal Transduction, Nucleic Acids Encoding Same and Methods of Use Thereof - A method of modulating immune response in an animal is disclosed. Such a method interacting the immature dendritic cells from the animal with an antigen ex vivo so that the immature dendritic cells present the antigen on their surfaces, inducing maturation of the immature dendritic cells ex vivo, and contacting the mature dendritic cells ex vivo with a modulator comprising TRANCE, conservative variants thereof, fragments thereof, analogs or derivatives thereof, or a fusion protein comprising the amino acid sequence of TRANCE, conservative variants thereof, or fragments thereof. After contacting the modulator ex vivo, the mature dendritic cells are introduced into the animal. As a result, immune response in the animal towards the antigen is modulated relative to the immune response against the antigen in an animal in which dendritic cells did not interact with the antigen ex vivo, and did not contact a modulator ex vivo. Preferably, the method of the present invention results in increasing immune response towards the antigen in the animal. | 03-14-2013 |
20150056184 | Protein Belonging to the TNF Superfamily Involved in Signal Transduction, Nucleic Acids Encoding Same and Methods of Use Thereof - A method of modulating immune response in an animal is disclosed. Such a method interacting the immature dendritic cells from the animal with an antigen ex vivo so that the immature dendritic cells present the antigen on their surfaces, inducing maturation of the immature dendritic cells ex vivo, and contacting the mature dendritic cells ex vivo with a modulator comprising TRANCE, conservative variants thereof, fragments thereof, analogs or derivatives thereof, or a fusion protein comprising the amino acid sequence of TRANCE, conservative variants thereof, or fragments thereof. After contacting the modulator ex vivo, the mature dendritic cells are introduced into the animal. As a result, immune response in the animal towards the antigen is modulated relative to the immune response against the antigen in an animal in which dendritic cells did not interact with the antigen ex vivo, and did not contact a modulator ex vivo. Preferably, the method of the present invention results in increasing immune response towards the antigen in the animal. | 02-26-2015 |
Patent application number | Description | Published |
20080199123 | ULTRAFAST GE/SI RESONATOR-BASED MODULATORS FOR OPTICAL DATA COMMUNICATIONS IN SILICON PHOTONICS - An optical modulator structure includes at least two waveguide structures for inputting and outputting an optical signal. At least one ring resonator structure provides coupling between the at least two waveguide structures. The at least one ring resonator structure includes Ge or SiGe. | 08-21-2008 |
20080224121 | SPONTANEOUS EMISSION OF TELECOMMUNICATION WAVELENGTH EMITTERS COUPLED TO AT LEAST ONE RESONANT CAVITY - Systems and methods for devices that include a structure having at least one resonant cavity and at least one emitter having an emission frequency that is substantially in the telecommunication wavelengths are provided. The emission frequency can be coupled to the resonant frequency of resonant cavity so that emitted wavelengths corresponding to the resonant wavelengths of the resonant cavity are enhanced. Moreover, the devices of the present invention may be capable of operating at room temperatures. | 09-18-2008 |
20080315177 | LIGHT EMISSION USING QUANTUM DOT EMITTERS IN A PHOTONIC CRYSTAL - Devices and methods of manufacturing; for emitting substantially white light using a photonic crystal are described. The photonic crystal has a lattice of air holes and is made from a substrate containing quantum dots. The substrate is etched with three defects that are optically coupled together so that each emits only certain frequencies of light. In combination, the defects can produce substantially white light. The parameters of the photonic crystal are dimensioned so as to cause the coupling between the defects to produce substantially white light. | 12-25-2008 |
20090092156 | DEVICES AND METHODS FOR PROVIDING STIMULATED RAMAN LASING - Devices and methods for providing stimulated Raman lasing are provided. In some embodiments, devices include a photonic crystal that includes a layer of silicon having a lattice of holes and a linear defect that forms a waveguide configured to receive pump light and output Stokes light through Raman scattering, wherein the thickness of the layer of silicon, the spacing of the lattice of holes, and the size of the holes are dimensioned to provide Raman lasing. In some embodiments, methods include forming a layer of silicon, and etching the layer of silicon to form a lattice of holes with a linear defect that forms a waveguide configured to receive pump light and output Stokes light through Raman scattering, wherein the thickness of the layer of silicon, the spacing of the lattice of holes, and the size of the holes are dimensioned to provide Raman lasing. | 04-09-2009 |
20090191657 | ALL-SILICON RAMAN AMPLIFIERS AND LASERS BASED ON MICRO RING RESONATORS - Methods of manufacturing a lasing device are provided by some embodiments, the methods including: creating a silicon micro ring with a predetermined radius and a predetermined first cross-sectional dimension; creating a silicon waveguide with a predetermined second cross-sectional dimension, the silicon waveguide spaced from the silicon micro ring by a predetermined distance; and wherein the predetermined distance, the predetermined radius, the predetermined first cross-sectional dimension, and the predetermined second cross-sectional dimension are determined so that at least one first whispering gallery mode resonant frequency of the silicon micro ring and at least one second whispering gallery mode resonant frequency of the silicon micro ring are separated by an optical phonon frequency of silicon. | 07-30-2009 |
20090269002 | SYSTEMS AND METHODS FOR SENSING PROPERTIES OF A WORKPIECE AND EMBEDDING A PHOTONIC SENSOR IN METAL - Systems and methods for sensing properties of a workpiece and embedding a photonic sensor in metal are disclosed herein. In some embodiments, systems for sensing properties of a workpiece include an optical input, a photonic device, an optical detector, and a digital processing device. The optical input provides an optical signal at an output of the optical input. The photonic device is coupled to the workpiece and to the output of the optical input. The photonic device generates an output signal in response to the optical signal, wherein at least one of an intensity of the output signal and a wavelength of the output signal depends on at least one of thermal characteristics and mechanical characteristics of the workpiece. The optical detector receives the output signal from the photonic device and is configured to generate a corresponding electronic signal. The digital processing device is coupled to the optical detector and determines at least one of the thermal characteristics and mechanical the characteristics of the workpiece based on the electronic signal. | 10-29-2009 |
20100270481 | SYSTEMS, DEVICES AND METHODS FOR TUNING A RESONANT WAVELENGTH OF AN OPTICAL RESONATOR AND DISPERSION PROPERTIES OF A PHOTONIC CRYSTAL WAVEGUIDE - Some embodiments of the disclosed subject matter provide systems, devices, and methods for tuning resonant wavelengths of an optical resonator. Some embodiments of the disclosed subject matter provide systems, devices, and methods for tuning dispersion properties of photonic crystal waveguides. In some embodiments, methods for tuning a resonant wavelength of an optical resonator are provided, the methods including: providing an optical resonator having a surface; determining an initial resonant wavelength emitted by the optical resonator in response to an electromagnetic radiation input; determining a number of layers of dielectric material based on a difference between the initial resonant wavelength and a target resonant wavelength and a predetermined tuning characteristic; and applying the determined number of layers of dielectric material to the surface of the optical resonator to tune the initial resonant wavelength to a tuned resonant wavelength. | 10-28-2010 |
20110147344 | DEVICES AND METHODS FOR PROVIDING STIMULATED RAMAN LASING - Devices and methods for providing stimulated Raman lasing are provided. In some embodiments, devices include a photonic crystal that includes a layer of silicon having a lattice of holes and a linear defect that forms a waveguide configured to receive pump light and output Stokes light through Raman scattering, wherein the thickness of the layer of silicon, the spacing of the lattice of holes, and the size of the holes are dimensioned to provide Raman lasing. In some embodiments, methods include forming a layer of silicon, and etching the layer of silicon to form a lattice of holes with a linear defect that forms a waveguide configured to receive pump light and output Stokes light through Raman scattering, wherein the thickness of the layer of silicon, the spacing of the lattice of holes, and the size of the holes are dimensioned to provide Raman lasing. | 06-23-2011 |
20110249689 | DEVICES, SYSTEMS, AND METHODS PROVIDING MICRO-RING AND/OR MICRO-RACETRACK RESONATOR - Provided herein are certain embodiments of systems, methods and devices for Raman lasers based on micro-ring and mircro-racetrack resonators, and the manufacturing thereof. For example, a device can be provided which is structured to receive an electro-magnetic radiation including a resonator arrangement which has a distance from one edge thereof to another edge thereof of at most approximately a wavelength of the electro-magnetic radiation that impacts the resonator arrangement. According to some embodiments, the resonator arrangement can be configured to generate a Raman radiation when impacted by a further electro-magnetic radiation. In some embodiments, the resonator arrangement can solely generate the Raman radiation which is lasing, which Raman radiation can be generated by the resonator arrangement in a continuous mode and/or a pulsed lasing mode. The resonator arrangement can generate the Raman radiation which is lasing without a use of an external electrical driver. | 10-13-2011 |
20140158871 | SYSTEMS AND METHODS FOR SENSING PROPERTIES OF A WORKPIECE AND EMBEDDING A PHOTONIC SENSOR IN METAL - Systems and methods for sensing properties of a workpiece and embedding a photonic sensor in metal are disclosed herein. In some embodiments, systems for sensing properties of a workpiece include an optical input, a photonic device, an optical detector, and a digital processing device. The optical input provides an optical signal at an output of the optical input. The photonic device is coupled to the workpiece and to the output of the optical input. The photonic device generates an output signal in response to the optical signal, wherein at least one of an intensity of the output signal and a wavelength of the output signal depends on at least one of thermal characteristics and mechanical characteristics of the workpiece. The optical detector receives the output signal from the photonic device and is configured to generate a corresponding electronic signal. The digital processing device is coupled to the optical detector and determines at least one of the thermal characteristics and mechanical the characteristics of the workpiece based on the electronic signal. | 06-12-2014 |
Patent application number | Description | Published |
20140131777 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SALICIDE CONTACTS ON NON-PLANAR SOURCE/DRAIN REGIONS - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a fin over a semiconductor substrate. The method further includes selectively epitaxially growing a silicon-containing material on the fin and providing the fin with a diamond-shaped cross-section and with an upper portion and a lower portion. The lower portion of the fin is covered with a masking layer. Further, a salicide layer is formed on the upper portion of the fin, and the masking layer prevents formation of the salicide layer on the lower portion of the fin. | 05-15-2014 |
20140134814 | METHODS OF MANUFACTURING INTEGRATED CIRCUITS HAVING FINFET STRUCTURES WITH EPITAXIALLY FORMED SOURCE/DRAIN REGIONS - Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. For example, a method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, forming disposable spacers on vertical sidewalls of the fin structures, and depositing a silicon oxide material over the fins and over the disposable spacers. The method further includes anisotropically etching at least one of the fin structures and the disposable spacers on the sidewalls of the at least one fin structure, thereby leaving a void in the silicon oxide material, and etching the silicon oxide material and the disposable spacers from at least one other of the fin structures, while leaving the at least one other fin structure un-etched. Still further, the method includes epitaxially growing a silicon material in the void and on the un-etched fin structure. An un-merged source/drain region is formed in the void and a merged source/drain region is formed on the un-etched fin structure. | 05-15-2014 |
20140256141 | METHODS FOR FABRICATING INTEGRATED CIRCUITS UTILIZING SILICON NITRIDE LAYERS - A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles. | 09-11-2014 |
20140264489 | WRAP AROUND STRESSOR FORMATION - For the formation of a stressor on one or more of a source and drain defined on a fin of FINFET semiconductor structure, a method can be employed including performing selective epitaxial growth (SEG) on one or more of the source and drain defined on the fin, separating the fin from a bulk silicon substrate at one or more of the source and drain, and further performing SEG on one or more of the source and drain to form a wrap around epitaxial growth stressor that stresses a channel connecting the source and drain. The formed stressor can be formed so that the epitaxial growth material defining a wrap around configuration connects to the bulk substrate. The formed stressor can increase mobility in a channel connecting the defined source and drain. | 09-18-2014 |
20140319615 | FINFET WITH ACTIVE REGION SHAPED STRUCTURES AND CHANNEL SEPARATION - A semiconductor structure in fabrication includes a n-FinFET and p-FinFET. Stress inducing materials such as silicon and silicon germanium are epitaxially grown into naturally diamond-shaped structures atop the silicon fins of the n-FinFET and p-FinFET areas. The diamond structures act as the source, drain and channel between the source and drain. The diamond structures of the channel are selectively separated from the fin while retaining the fin connections of the diamond-shaped growth of the source and the drain. Further fabrication to complete the structure may then proceed. | 10-30-2014 |
20150021694 | INTEGRATED CIRCUITS HAVING REPLACEMENT METAL GATES WITH IMPROVED THRESHOLD VOLTAGE PERFORMANCE AND METHODS FOR FABRICATING THE SAME - Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a chamfered surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench. | 01-22-2015 |
20150099336 | METHODS OF MANUFACTURING INTEGRATED CIRCUITS HAVING FINFET STRUCTURES WITH EPITAXIALLY FORMED SOURCE/DRAIN REGIONS - Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. A method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, epitaxially growing a silicon material on the fin structures, wherein a merged source/drain region is formed on the fin structures, and anisotropically etching at least one of the merged source drain regions to form an un-merged source/drain region. | 04-09-2015 |
20150187947 | FINFET WITH ACTIVE REGION SHAPED STRUCTURES AND CHANNEL SEPARATION - A semiconductor structure in fabrication includes a n-FinFET and p-FinFET. Stress inducing materials such as silicon and silicon germanium are epitaxially grown into naturally diamond-shaped structures atop the silicon fins of the n-FinFET and p-FinFET areas. The diamond structures act as the source, drain and channel between the source and drain. The diamond structures of the channel are selectively separated from the fin while retaining the fin connections of the diamond-shaped growth of the source and the drain. Further fabrication to complete the structure may then proceed. | 07-02-2015 |
20150221726 | FINFET WITH ISOLATED SOURCE AND DRAIN - A FinFET has shaped epitaxial structures for the source and drain that are electrically isolated from the substrate. Shaped epitaxial structures in the active region are separated from the substrate in the source and drain regions while those in the channel region remain. The gaps created by the separation in the source and drain are filled with electrically insulating material. Prior to filling the gaps, defects created by the separation may be reduced. | 08-06-2015 |
Patent application number | Description | Published |
20110289117 | SYSTEMS AND METHODS FOR USER CONTROLLABLE, AUTOMATED RECORDING AND SEARCHING OF COMPUTER ACTIVITY - Systems and methods for automating the process of recording, indexing, and searching computer activity are provided. Events resulting from computer activities trigger capturing of contents and association of operational contextual information to form a searchable record of activities. The searchable record can be stored in local computer for use by its user, or on server computer, such as can be used for a tutorial by multiple users. Storage management can be used to manage the storage requirements of the captured information forming the searchable record. | 11-24-2011 |
20120258727 | Mechanism for Content Management in Wireless Mobile Networks - Techniques for content management in wireless mobile networks are provided. In one aspect, a method of managing content stored on a plurality of mobile nodes in a mobile ad hoc network (MANET) is provided. The method includes the following step. The content is bound to one or more geographical locations such that, at any given time, the content is stored on at least one of the nodes at the geographical location. | 10-11-2012 |
20120294187 | ASSIGNING GATEWAYS FOR HETEROGENEOUS WIRELESS MOBILE NETWORKS - Systems and methods are provided for assigning gateways for heterogeneous wireless mobile networks. A method includes exchanging routing and connectivity information between a plurality of nodes. Each node is respectively included in a corresponding one of a plurality of mobile ad hoc networks. The information excludes global positioning satellite information. The method further includes determining, for a given node, whether a particular set of gateway functionalities of the given node are redundant with respect to one or more other nodes, based on topology information derived from the information. The method also includes dynamically assigning the given node as a gateway or a non-gateway by respectively turning on or turning off the particular set of gateway functionalities of the given node when the particular set of gateway functionalities of the given node are respectively determined to be non-redundant or redundant with respect to the one or more other nodes. | 11-22-2012 |
20140040693 | Rate Adaptive Transmission of Wireless Broadcast Packets - Mechanisms are provided for broadcasting data to a plurality of receiver devices. A data broadcast transmission rate and a level of error correction to be used when broadcasting data are determined based on prior feedback received from the plurality of receiver devices. The feedback comprises channel condition information specifying conditions of one or more connections of a channel over which data was previously broadcast to the receiver devices. Data to be broadcast to the plurality of receivers is encoded in accordance with the determined level of error correction. The encoded data is broadcast at the determined data broadcast transmission rate over the channel to the plurality of receiver devices. | 02-06-2014 |
20140105005 | PERFORMING VALUE AND CONTEXT AWARE COMMUNICATIONS NETWORKING - An aspect of this invention is a computer-executable method for distributing one or more features associated with information to be transported by a communications network that includes a plurality of end nodes interconnected via a plurality of network nodes. The method includes receiving one or more features associated with information to be transported by the communications network, wherein the one or more features are specified at an end node of the plurality of end nodes for receipt by a network node of the plurality of network nodes; responsive to the one or more received features, configuring at least a portion of the communications network to perform actions on information based upon the features; receiving the information using the plurality of network nodes; and based at least on the received features and the configuring, performing one or more actions with the information. Illustratively, the one or more actions comprise sending the information to one or more edge entity nodes in accordance with the configuring and the received features. | 04-17-2014 |
20140108626 | Virtual Consolidated Appliance - Techniques for managing network traffic in a virtual consolidated appliance so as to avoid interruptions in existing network connections during reconfiguration of the virtual consolidated appliance are provided. In one aspect, a method for operating a virtual consolidated appliance having a plurality of servers is provided. The method includes the following steps. An assignment for load balancing is computed based on a status of the virtual consolidated appliance. A reconfiguration of the virtual consolidated appliance is discovered. A new assignment is computed for load balancing based on a new status of the virtual consolidated appliance based on the reconfiguration of the virtual consolidated appliance. Existing network connections are redirected according to the assignment during the reconfiguration of the virtual consolidated appliance. New network connections are served according to the new assignment. | 04-17-2014 |
20140126378 | Wireless Network Optimization Appliance - Methods and apparatus are provided for wireless network optimization. Wireless network traffic is optimized by receiving redirected traffic based on one or more configuration rules; and applying the redirected traffic to a protocol optimizer that optimizes the wireless network traffic based on one or more optimization rules. A management interface is optionally provided to manage the network optimization appliance. A process monitor is optionally provided to monitor one or more process threads to determine if the process threads have stalled. The process monitor can monitor other components and can be monitored by at least one other component. | 05-08-2014 |
20140126379 | Wireless Network Optimization Appliance - Methods and apparatus are provided for wireless network optimization. Wireless network traffic is optimized by receiving redirected traffic based on one or more configuration rules; and applying the redirected traffic to a protocol optimizer that optimizes the wireless network traffic based on one or more optimization rules. A management interface is optionally provided to manage the network optimization appliance. A process monitor is optionally provided to monitor one or more process threads to determine if the process threads have stalled. The process monitor can monitor other components and can be monitored by at least one other component. | 05-08-2014 |
20140133348 | PERFORMING VALUE AND CONTEXT AWARE COMMUNICATIONS NETWORKING - An aspect of this invention is a computer-executable method for distributing one or more features associated with information to be transported by a communications network that includes a plurality of end nodes interconnected via a plurality of network nodes. The method includes receiving one or more features associated with information to be transported by the communications network, wherein the one or more features are specified at an end node of the plurality of end nodes for receipt by a network node of the plurality of network nodes; responsive to the one or more received features, configuring at least a portion of the communications network to perform actions on information based upon the features; receiving the information using the plurality of network nodes; and based at least on the received features and the configuring, performing one or more actions with the information. Illustratively, the one or more actions comprise sending the information to one or more edge entity nodes in accordance with the configuring and the received features. | 05-15-2014 |
20140325302 | Reliable Multicast Broadcast in Wireless Networks - A mechanism is provided for transmitting a multicast session to a plurality of receivers over a wireless network. A forward error correction (FEC) overhead and a transmission rate are determined for transmission of a next data block of the multicast session based on received channel conditions. The next data block is multicast using the determined FEC overhead and transmission rate. Responsive to an indication of common missing packets from the next data block from more than one receiver in the plurality of receivers, the common missing packets are multicast to the plurality of receivers using the determined FEC overhead and transmission rate. Responsive to an indication of uncommon missing packets from the data block from one or more receivers, for each receiver in the one or more receivers, the uncommon missing packets identified by the receiver are unicast using the determined FEC overhead and transmission rate. | 10-30-2014 |
20140325505 | Bandwidth-Efficient Virtual Machine Image Delivery - A mechanism is provided for bandwidth-efficient virtual machine image delivery. Responsive to a request to generate a virtual machine (VM) in a node using an existing virtual machine image (VMI) file, a set of file chunks that constitute the VMI file is identified. The set of file chunks are retrieved from within a set of distributed nodes by establishing an optimized plan for retrieving the set of file chunks in a bandwidth-efficient manner. Responsive to retrieving the set of file chunks from within the distributed nodes, the set of file chunks are reassembled into the VMI file for generation of the VM. | 10-30-2014 |
20140325507 | Bandwidth-Efficient Virtual Machine Image Delivery - A mechanism is provided for bandwidth-efficient virtual machine image delivery. Responsive to a request to generate a virtual machine (VM) in a node using an existing virtual machine image (VMI) file, a set of file chunks that constitute the VMI file is identified. The set of file chunks are retrieved from within a set of distributed nodes by establishing an optimized plan for retrieving the set of file chunks in a bandwidth-efficient manner. Responsive to retrieving the set of file chunks from within the distributed nodes, the set of file chunks are reassembled into the VMI file for generation of the VM. | 10-30-2014 |
20140348049 | Rate Adaptive Transmission of Wireless Broadcast Packets - Mechanisms are provided for broadcasting data to a plurality of receiver devices. A data broadcast transmission rate and a level of error correction to be used when broadcasting data are determined based on prior feedback received from the plurality of receiver devices. The feedback comprises channel condition information specifying conditions of one or more connections of a channel over which data was previously broadcast to the receiver devices. Data to be broadcast to the plurality of receivers is encoded in accordance with the determined level of error correction. The encoded data is broadcast at the determined data broadcast transmission rate over the channel to the plurality of receiver devices. | 11-27-2014 |
Patent application number | Description | Published |
20140188501 | APPARATUS AND METHOD FOR EXECUTING TASKS - An apparatus for executing a task includes an authenticator to identify a user, a controller that can receive data from the user, and an authorizer to ensure that the user has access to applications used to execute the task. The controller is able to register or de-register the applications and then determine which if the registered applications should be used to execute the task. The controller then converts the data from the user so that it can be used by the application to execute the task. If the user selects a second task to be executed, the controller can determine which of the registered applications is to be used to execute the second task. Methods for executing multiple tasks are also described. | 07-03-2014 |
20140250427 | METHOD AND APPARATUS FOR PRODUCING REGULATORY-COMPLIANT SOFTWARE - A method for producing regulatory-compliant software includes validating a software application and freezing the validated software application in a validation portal, proving-in an infrastructure on which the software application operates, and providing evidence of operational change management for a regulatory agency, which evidence comprises documentation that satisfies the agency's compliance rules. A regulatory-compliant software package is also described. | 09-04-2014 |
20150106116 | SYSTEM AND METHOD FOR OBTAINING AND UTILIZING AUDITS FROM DISPARATE SOURCES - Disparate (heterogeneous) clinical data recording devices are assimilated into a unified clinical system that is able to function regardless of the disparate data protocols of the recording devices. The unified system is realized in some embodiments by cascading a consistent set of audits generated by the recording devices through downstream clinical components, which audits provide a permanent and indelible record. The cascaded audits may also serve as a means of instruction between the disparate components of a unified clinical system. | 04-16-2015 |
20150143480 | METHOD AND SYSTEM FOR MAINTAINING DATA IN A SUBSTANTIATED STATE - A method for substantiating a data message for use in a system includes adding discovery information to the data message related to the origin of the data message, validating the data message to comply with an industry standard, authenticating the data message to determine who transmitted the data message, and authorizing the transmission of the data message based on access rights. A method for generating a substantiated system is also described. | 05-21-2015 |
20150269326 | SYSTEM AND METHOD FOR PRESERVING CAUSALITY OF AUDITS - A system for preserving causality of audits may include an upstream service, a downstream service, and an audit service. The upstream service receives a first request including a trace ID and a first span ID, generates a first audit concerning a resource owned by the upstream service and having the trace ID and the first span ID as metadata, persists the first audit to a first database, and generates a second request including the trace ID, a parent span ID, and a second span ID. The downstream service receives the second request from the upstream service, generates a second audit concerning a resource owned by the downstream service and having the trace ID, second span ID, and parent span ID as metadata, and persists the second audit to a second database. The audit service receives and asynchronously centralizes the first and second audits. The metadata can be used to infer causality of the audits. A method for preserving causality of audits is also disclosed and claimed. | 09-24-2015 |
Patent application number | Description | Published |
20110260323 | HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT - The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing. | 10-27-2011 |
20120061798 | HIGH CAPACITANCE TRENCH CAPACITOR - A dual node dielectric trench capacitor includes a stack of layers formed in a trench. The stack of layers include, from bottom to top, a first conductive layer, a first node dielectric layer, a second conductive layer, a second node dielectric layer, and a third conductive layer. The dual node dielectric trench capacitor includes two back-to-back capacitors, which include a first capacitor and a second capacitor. The first capacitor includes the first conductive layer, the first node dielectric layer, the second conductive layer, and the second capacitor includes the second conductive layer, the second node dielectric layer, and the third conductive layer. The dual node dielectric trench capacitor can provide about twice the capacitance of a trench capacitor employing a single node dielectric layer having a comparable composition and thickness as the first and second node dielectric layers. | 03-15-2012 |
20130037865 | SEMICONDUCTOR STRUCTURE HAVING A WETTING LAYER - A semiconductor structure which includes a semiconductor substrate and a metal gate structure formed in a trench or via on the semiconductor substrate. The metal gate structure includes a gate dielectric; a wetting layer selected from the group consisting of cobalt and nickel on the gate dielectric lining the trench or via and having an oxygen content of no more than about 200 ppm (parts per million) oxygen; and an aluminum layer to fill the remainder of the trench or via. There is also disclosed a method of forming a semiconductor structure in which a wetting layer is formed from cobalt amidinate or nickel amidinate deposited by a chemical vapor deposition process. | 02-14-2013 |
Patent application number | Description | Published |
20140312412 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer. | 10-23-2014 |
20140312413 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions a gate structure embedded in a substrate; self-aligned source and drain contacts embedded in the substrate around the gate structure; and a channel layer over the gate structure and self-aligned source and drain contacts. The source and drain contacts extend above the channel layer. | 10-23-2014 |
20140332860 | STACKED CARBON-BASED FETS - Methods and systems for forming stacked transistors. Such methods include forming a lower channel layer on a substrate; forming a pair of vertically aligned gate regions over the lower channel layer; forming a pair of vertically aligned source regions and a pair of vertically aligned drain regions on the lower channel material, each pair separated by an insulator; forming an upper channel material over the source regions, drain regions, and gate regions; and providing electrical access to the source, drain, and gate regions. | 11-13-2014 |
20140332862 | STACKED CARBON-BASED FETS - Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where the pair of drain regions are separated by an insulator; a pair of vertically aligned gate regions formed on the lower gate dielectric layer; and an upper channel layer formed over the source regions, drain regions, and gate regions. | 11-13-2014 |
20150187764 | STACKED CARBON-BASED FETS - A stacked transistor device includes a lower transistor that has a lower channel layer formed on a substrate and lower source and drain regions formed directly over the lower channel layer. The lower source and drain regions are in electrical contact with respective conductive source and drain extensions formed in the substrate. An upper transistor has upper source and drain regions vertically aligned with the respective lower source and drain regions. The upper source and drain regions are separated from the respective lower source and drain regions by an insulator. The upper transistor further includes an upper channel layer formed over the upper source and drain regions. | 07-02-2015 |
20150228753 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses. The source and drain contacts extend above the channel layer. | 08-13-2015 |
Patent application number | Description | Published |
20090302405 | METHOD FOR FORMING SLOT VIA BITLINE FOR MRAM DEVICES - A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask. | 12-10-2009 |
20110012629 | REPLACEMENT-GATE-COMPATIBLE PROGRAMMABLE ELECTRICAL ANTIFUSE - After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state). | 01-20-2011 |
20110042786 | INTEGRATION OF PASSIVE DEVICE STRUCTURES WITH METAL GATE LAYERS - A passive device structure includes an unpatterned metal gate layer formed in a passive device region of a semiconductor device; an insulator layer formed upon the unpatterned metal gate layer; a semiconductor layer formed upon the insulator layer; and one or more metal contact regions formed in the semiconductor layer; wherein the insulator layer prevents the metal gate layer as serving as a leakage current path for current flowing through a passive device defined by the semiconductor layer and the one or more metal contact regions. | 02-24-2011 |
20110079874 | ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION - An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material. | 04-07-2011 |
20110083786 | ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES - An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded. | 04-14-2011 |
20110095379 | SCALING OF METAL GATE WITH ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT - A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided. | 04-28-2011 |
20110127637 | Nanopillar E-Fuse Structure and Process - Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure. | 06-02-2011 |
20110215409 | STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL - An electrical device is provided with a p-type semiconductor device having a first gate structure that includes a gate dielectric on top of a semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure. | 09-08-2011 |
20110254098 | INTEGRATED CIRCUIT WITH REPLACEMENT METAL GATES AND DUAL DIELECTRICS - A replacement gate structure and method of fabrication are disclosed. The method provides for fabrication of both high performance FET and low leakage FET devices within the same integrated circuit. Low leakage FET devices are fabricated with a hybrid gate dielectric comprised of a low-K dielectric layer and a high-K dielectric layer. High performance FET devices are fabricated with a low-K gate dielectric. | 10-20-2011 |
20120061772 | Transistor having replacement metal gate and process for fabricating the same - A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor. | 03-15-2012 |
20120122280 | ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION - An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material. | 05-17-2012 |
20120126366 | ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION - An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material. | 05-24-2012 |
20120126367 | ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION - An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material. | 05-24-2012 |
20120129340 | ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION - An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material. | 05-24-2012 |
20120190203 | METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION - Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well. | 07-26-2012 |
20140035068 | Transistor having replacement metal gate and process for fabricating the same - A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor. | 02-06-2014 |
Patent application number | Description | Published |
20120300790 | MEMORY SAVING PACKET MODIFICATION - The method includes creating a master copy of a header for all packets of a data transmission event, the master copy including a plurality of intact constant header information, the plurality of intact constant header information being constant for all packets of the data transmission event, storing unique header information for all packets of the data transmission event, the unique header information including information unique to at least one packet of the data transmission event, tokenizing identities of each packet of the data transmission event to create a tokenized packet ID for each packet, and indexing the stored unique header information based on the tokenizing. A computer program product for directing a computer processor to perform a method. According to the method, at packet read-time, unique header information associated with the packet is overlayed onto the master copy to create a unique packet. | 11-29-2012 |
20120304040 | CHECKSUM CALCULATION, PREDICTION AND VALIDATION - A checksum calculation, prediction and validation system includes a host system, a network interface, a reception pipeline disposed between the host system and network interface and configured to calculate an expected full checksum related to packets received in the host system and a transmission pipeline disposed between the host system and network interface and configured calculate factors related to packets for transmission on the network interface. | 11-29-2012 |
20130042168 | CHECKSUM CALCULATION, PREDICTION AND VALIDATION - A calculation, prediction and validation method can include receiving a portion of a data packet in a data buffer, computing, in a processor, information related to the checksum of the data packet based on the portion of the data packet and processing the data packet in the processor. | 02-14-2013 |
20130070771 | Memory Saving Packet Modification - A computer-implemented method that includes creating a master copy of a header for all packets of a data transmission event, the master copy including a plurality of intact constant header information, the plurality of intact constant header information being constant for all packets of the data transmission event, storing unique header information for all packets of the data transmission event, the unique header information including information unique to at least one packet of the data transmission event, tokenizing identities of each packet of the data transmission event to create a tokenized packet ID for each packet, and indexing the stored unique header information based on the tokenizing. According to the method, at packet read-time, unique header information associated with the packet is overlayed onto the master copy to create a unique packet. | 03-21-2013 |
20140047307 | CHECKSUM CALCULATION, PREDICTION AND VALIDATION - A calculation, prediction and validation method can include receiving a portion of a data packet in a data buffer, computing, in a processor, information related to the checksum of the data packet based on the portion of the data packet and processing the data packet in the processor. | 02-13-2014 |
Patent application number | Description | Published |
20110193024 | Metal sulfide and rare-earth phosphate nanostructures and methods of making same - The present invention provides a method of producing a crystalline metal sulfide nanostructure. The method comprising: providing a metal precursor solution and providing a sulfur precursor solution; placing a porous membrane between the metal precursor solution and the sulfur precursor solution, wherein metal cations of the metal precursor solution and sulfur ions of the sulfur precursor solution react, thereby producing a crystalline metal sulfide nanostructure, wherein the metal is a transitional metal or a Group IV metal. | 08-11-2011 |
20120088656 | NANOSTRUCTURES HAVING ENHANCED CATALYTIC PERFORMANCE AND METHOD FOR PREPARING SAME - Provided herein is a nanostructure refined by suspending an unrefined nanostructure with a solvent, dispersing the suspended nanostructure in an acidic solution and agitating the acidic solution to produce a refined nanostructure. | 04-12-2012 |
20130178357 | Method for Removing Strongly Adsorbed Surfactants and Capping Agents from Metal to Facilitate their Catalytic Applications - A method of synthesizing activated electrocatalyst, preferably having a morphology of a nanostructure, is disclosed. The method includes safely and efficiently removing surfactants and capping agents from the surface of the metal structures. With regard to metal nanoparticles, the method includes synthesis of nanoparticle(s) in polar or non-polar solution with surfactants or capping agents and subsequent activation by CO-adsorption-induced surfactant/capping agent desorption and electrochemical oxidation. The method produces activated macroparticle or nanoparticle electrocatalysts without damaging the surface of the electrocatalyst that includes breaking, increasing particle thickness or increasing the number of low coordination sites. | 07-11-2013 |
20140065437 | SEGMENTED METALLIC NANOSTRUCTURES, HOMOGENEOUS METALLIC NANOSTRUCTURES AND METHODS FOR PRODUCING SAME - The present invention includes a method of producing a segmented 1D nanostructure. The method includes providing a vessel containing a template wherein on one side of the template is a first metal reagent solution and on the other side of the template is a reducing agent solution, wherein the template comprises at least one pore; allowing a first segment of a 1D nanostructure to grow within a pore of the template until a desired length is reached; replacing the first metal reagent solution with a second metal reagent solution; allowing a second segment of a 1D nanostructure to grow from the first segment until a desired length is reached, wherein a segmented 1D nanostructure is produced. | 03-06-2014 |