Patent application number | Description | Published |
20090097306 | Phase-change random access memory device, system having the same, and associated methods - A phase-change random access memory (PRAM) device includes a PRAM cell array including a first sector and a second sector, a first global bit line coupled to a first local bit line of the first sector and a first local bit line of the second sector, and a first plurality of global bit line discharge units coupled to the first global bit line, the first plurality of global bit line discharge units configured to discharge the first global bit line in response to a first global discharge signal. | 04-16-2009 |
20090122601 | POWER SUPPLYING CIRCUIT AND PHASE-CHANGE RANDOM ACCESS MEMORY INCLUDING THE SAME - Embodiments of the invention provide a power supplying circuit (PSC) and a phase-change random access memory (PRAM) including the PSC. According to an aspect of the invention, the PSC includes: a first voltage generator configured to output a first voltage to a first terminal; and a second voltage generator configured to output a second voltage to a second terminal, the second voltage generator including: a voltage pump unit configured to output the second voltage based on a clock signal and a pump control signal; a pump output detector coupled to the voltage pump unit, the pump output detector configured to output a pump output detection signal; and a discharging unit coupled to the voltage pump unit, the discharging unit configured to discharge a level of the second voltage to a predetermined level in response to a discharge signal. Embodiments of the invention may prevent write and/or read malfunctions that can occur due to changes in the level of a voltage supplied to PRAM cell blocks. | 05-14-2009 |
20090164722 | Memory card and memory storage device using the same - A memory card and a memory storage device using the memory card may be provided. The memory card may include a host connector, a memory controller connected to the host connector and enabled or disabled in response to a capacity expansion signal, a non-volatile memory connected to the memory controller, a memory connector configured to connect to the memory controller and the non-volatile memory, and a capacity expansion switch configured to generate the capacity expansion signal. Accordingly, when the memory cards are connected to increase storage capacity, only a memory controller of one memory card may operate, thereby reducing power consumption. | 06-25-2009 |
20090164723 | Memory card - The memory card includes a memory controller covered by a main body, a first non-volatile memory, a memory interface configured to transfer a signal between the memory controller and the first non-volatile memory, and a cover coupled to the main body and removeably covering the first memory and the memory interface. Here, the memory interface includes a connection detector configured to generate a connection detector signal when sensing that a package including a second non-volatile memory is added. | 06-25-2009 |
20110209030 | SEMICONDUCTOR MEMORY DEVICE AND DATA ERROR DETECTION AND CORRECTION METHOD OF THE SAME - A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data. | 08-25-2011 |
20110228581 | STACKED MEMORY DEVICE AND METHOD OF REPAIRING SAME - A stacked semiconductor memory device comprises memory cell array layers that are stacked in an inverted wedge shape and have different redundancy sizes from each other. The stacked semiconductor memory device has space for vertical connection between layers, a relatively small size, and a relatively high yield. | 09-22-2011 |
20130340068 | MEMORY DEVICE COMPRISING A PLURALITY OF MEMORY CHIPS, AUTHENTICATION SYSTEM AND AUTHENTICATION METHOD THEREOF - A memory device includes a plurality of memory chips, including one or more memory chips that store authentication information, and a controller including a first register that stores information indicating a representative memory chip, from among the one or more memory chips that store the authentication information, that stores valid authentication information. | 12-19-2013 |
20140157030 | SYSTEMS HAVING A MAXIMUM SLEEP MODE AND METHOD OF OPERATING THE SAME - A main memory system includes a main memory device including a first memory device implemented with a volatile memory and a second memory device implemented with a non-volatile memory, the main memory system being configured such that, when entering a sleep mode, the memory device reads a portion of data stored in the first memory device to store the read data in the second memory device, and, after the portion of data is read, the first memory device and the second memory device are powered off. | 06-05-2014 |