Patent application number | Description | Published |
20080259688 | Non-volatile memory devices and methods of operating the same - A non-volatile memory device includes memory transistors disposed on a semiconductor substrate in a NAND string. A string select transistor is disposed at a first end of the NAND string, and a ground select transistor is disposed at a second end of the NAN string. Bit lines are electrically connected to the semiconductor substrate outside of the string select transistor and a gate electrode of the ground select transistor. | 10-23-2008 |
20080315285 | Non-volatile memory devices and methods of fabricating the same - Non-volatile memory devices and methods of fabricating the same are provided. The non-volatile memory devices may include a semiconductor substrate having a pair of sidewall channel regions extending from the semiconductor substrate and opposite to each other, and a floating gate electrode between the pair of sidewall channel regions and protruding from the semiconductor substrate. A control gate electrode may be formed on the semiconductor substrate and a portion of the floating gate electrode. | 12-25-2008 |
20090016107 | Methods of operating nonvolatile memory devices - Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is selected from a plurality of memory cells and the boosting voltage on the channel of the selected memory cell is induced by a channel voltage of at least one memory cell connected to the selected memory cell. | 01-15-2009 |
20090045450 | Non-volatile memory device and method of fabricating the same - Provided are a non-volatile memory device, which may have higher integration density, improved or optimal structure, and/or reduce or minimize interference between adjacent cells without using an SOI substrate, and a method of fabricating the non-volatile memory device. The non-volatile memory device may include: a semiconductor substrate comprising a body, and a pair of fins protruding from the body; a buried insulating layer filling between the pair of fins; a pair of floating gate electrodes on outer surfaces of the pair of fins to a height greater than that of the pair of fins; and a control gate electrode on the pair of floating gate electrodes. | 02-19-2009 |
20090091975 | Non-volatile memory device and operation method of the same - Provided are a non-volatile memory device and an operation method of the same. The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor. | 04-09-2009 |
20090096060 | Antifuse structures, antifuse array structures, methods of manufacturing the same - Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array. | 04-16-2009 |
20090097321 | Non-volatile memory device, method of operating the same, and method of fabricating the same - A non-volatile memory device may include at least one semiconductor layer, a plurality of control gate electrodes, a plurality of charge storage layers, at least one first auxiliary electrode, and/or at least one second auxiliary electrode. The plurality of control gate electrodes may be recessed into the semiconductor layer. The plurality of charge storage layers may be between the plurality of control gate electrodes and the semiconductor layer. The first and second auxiliary electrodes may be arranged to face each other. The plurality of control gate electrodes may be between the first and second auxiliary electrodes and capacitively coupled with the semiconductor layer. | 04-16-2009 |
20090109761 | Method of operating nonvolatile memory device - Provided is a method of operating a three-dimensional nonvolatile memory device which may increase the reliability and efficiency of the three-dimensional nonvolatile memory device. The method of operating a nonvolatile memory device may include: resetting the nonvolatile memory device by injecting charges into charge storage layers of a plurality of memory cells of a block; and setting the nonvolatile memory device by removing at least some of the charges injected into the charge storage layers of one or more memory cells selected from among the plurality of memory cells. | 04-30-2009 |
20090122613 | Non-volatile memory device and method of operating the same - A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings. | 05-14-2009 |
20090141547 | Non-volatile memory devices and methods of fabricating and using the same - Provided are a non-volatile memory device, which may have a stacked structure and may be easily integrated at increased density, and a method of fabricating and using the non-volatile memory device. The non-volatile memory device may include at least one pair of first electrode lines. At least one second electrode line may be between the at least one pair of first electrode lines. At least one data storage layer may be between the at least one pair of first electrode lines and the at least one second electrode line and may locally store a resistance change. | 06-04-2009 |
20090184360 | Non-volatile memory device and method of fabricating the same - Provided are a non-volatile memory device that may expand to a stacked structure and may be more easily highly integrated and an economical method of fabricating the non-volatile memory device. The non-volatile memory device may include at least one semiconductor column. At least one first control gate electrode may be arranged on a first side of the at least one semiconductor column. At least one second control gate electrode may be arranged on a second side of the at least one semiconductor column. A first charge storage layer may be between the at least one first control gate electrode and the at least one semiconductor column. A second charge storage layer may be between the at least one second control gate electrode and the at least one semiconductor column. | 07-23-2009 |
20090212320 | Semiconductor devices and semiconductor apparatuses including the same - Semiconductor devices and semiconductor apparatuses including the same are provided. The semiconductor devices include a body region disposed on a semiconductor substrate, gate patterns disposed on the semiconductor substrate and on opposing sides of the body region, and first and second impurity doped regions disposed on an upper surface of the body region. The gate patterns may be separated from the first and second impurity doped regions by, or greater than, a desired distance, such that the gate patterns do not to overlap the first and second impurity doped regions in a direction perpendicular to the first and second impurity doped regions. | 08-27-2009 |
20090212364 | Semiconductor substrates and manufacturing methods of the same - Semiconductor substrates and methods of manufacturing the same are provided. The semiconductor substrates include a substrate region, an insulation region and a floating body region. The insulation region is disposed on the substrate region. The floating body region is separated from the substrate region by the insulation region and is disposed on the insulation region. The substrate region and the floating body region are formed of materials having identical characteristics. The method of manufacturing the semiconductor substrate including forming at least one floating body pattern by etching a bulk substrate, separating the bulk substrate into a substrate region and a floating body region by etching a lower middle portion of the floating body pattern, and filling an insulating material between the floating body region and the substrate region. | 08-27-2009 |
20090230442 | Semiconductor apparatus and manufacturing method of the same - Provided is a semiconductor apparatus including a substrate region, an active region on the substrate region, a gate pattern on the active region, and first and second impurities-doped regions along both edges of the active region that do not overlap the gate pattern. The length of the first and second impurities-doped regions in the horizontal direction may be shorter than in the vertical direction. The first and second impurities-doped regions may be formed to be narrow along both edges of the active region so as not to overlap the gate pattern. | 09-17-2009 |
20090253255 | Semiconductor device having a pair of fins and method of manufacturing the same - Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins. | 10-08-2009 |
20090273054 | Non-volatile memory device and method of fabricating the same - A non-volatile memory device and methods of fabricating the device according to example embodiments involve a stacked layer structure. The non-volatile memory device may include at least one first horizontal electrode including a first sidewall and a second sidewall; at least one second horizontal electrode including a third sidewall and a fourth sidewall; wherein the third sidewall may be disposed to face the first sidewall; at least one vertical electrode may be interposed between the first sidewall and the third sidewall, in such a way as to cross or intersect each of the at least one first and second horizontal electrodes, and; at least one data storage layer that may be capable of locally storing a change of electrical resistance may be interposed where the at least one first horizontal electrode and the at least one vertical electrode cross or intersect and where the at least one horizontal electrode and the at least one vertical electrodes cross or intersect. | 11-05-2009 |
20090285027 | Non-volatile memory devices and methods of operating non-volatile memory devices - A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line. | 11-19-2009 |
20090315084 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SUBSTRATE - A semiconductor device includes a semiconductor substrate, a gate pattern disposed on the semiconductor substrate, a body region disposed on the gate pattern and a first impurity doping region and a second impurity doping region. The gate pattern is disposed below the body region and the first impurity doping region and the second impurity doping region. | 12-24-2009 |
20100027316 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A non-volatile memory device having a stack structure, and a method of operating the non-volatile memory device In which the non-volatile memory device includes a plurality of variable resistors arranged in at least one layer. At least one layer selection bit line and a plurality of bit lines coupled to the plurality of the variable resistors are provided. A plurality of selection transistors coupled between the plurality of the bit lines and the plurality of the variable resistors are provided. | 02-04-2010 |
20100038719 | Semiconductor apparatuses and methods of manufacturing the same - Disclosed are semiconductor apparatuses and methods of fabricating the same. According to the methods, the number of operations for fabricating the semiconductor apparatuses having a plurality of layers may be the same as the number of operations for fabricating a semiconductor apparatus having one layer. The semiconductor apparatuses may include first active regions extending in the same direction, in parallel, separated from each other and including first and second impurity doped regions on opposite ends of the first active regions from each other. The semiconductor apparatuses may further include second active regions on a layer above the first active regions, extending in the same direction as the first active regions, separated from each other, in parallel, and including first and second impurity doped regions on opposite ends of the second active regions from each other. | 02-18-2010 |
20100041224 | Non-volatile memory device and method of manufacturing the same - The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode. | 02-18-2010 |
20100097124 | Method of operating semiconductor device - Provided is a method of operating a semiconductor device, wherein an operating mode is set by adjusting timing of a voltage pulse or by adjusting a voltage level of the voltage pulse. | 04-22-2010 |
20100118623 | Method of operating semiconductor devices - A method of operating a semiconductor device including a memory cell of a 1-T DRAM is provided in which a gate voltage level in a hold mode is adjusted to adjust a data sensing margin of the semiconductor device. | 05-13-2010 |
20100118634 | Semiconductor apparatuses and methods of operating the same - A method of operating a semiconductor device is provided including applying a constant source voltage to a source line. | 05-13-2010 |
20100127759 | Method of operating semiconductor device - Provided is a method of operating a semiconductor device, in which a gate voltage or a drain voltage is adjusted in order to add carriers to or remove carriers from a body region, thereby realizing semiconductor having a plurality of data states. | 05-27-2010 |
20100133600 | Semiconductor devices having increased sensing margin - One transistor (1-T) dynamic random access memories (DRAM) having improved sensing margins that are relatively independent of the amount of carriers stored in a body region thereof. | 06-03-2010 |
20100133647 | Semiconductor devices and semiconductor device manufacturing methods - Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure. | 06-03-2010 |
20100135088 | Operation method of semiconductor device - Provided is a method of operating a semiconductor device, in which timing for switching each of a drain voltage pulse signal and a gate voltage pulse signal from a first state to a second state is controlled in an erase mode and a write mode. | 06-03-2010 |
20100177566 | Non-volatile memory device having stacked structure, and memory card and electronic system including the same - Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set. | 07-15-2010 |
20100296344 | Methods of operating nonvolatile memory devices - Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is selected from a plurality of memory cells and the boosting voltage on the channel of the selected memory cell is induced by a channel voltage of at least one memory cell connected to the selected memory cell. | 11-25-2010 |
20110121390 | Semiconductor substrates and manufacturing methods of the same - Semiconductor substrates and methods of manufacturing the same are provided. The semiconductor substrates include a substrate region, an insulation region and a floating body region. The insulation region is disposed on the substrate region. The floating body region is separated from the substrate region by the insulation region and is disposed on the insulation region. The substrate region and the floating body region are formed of materials having identical characteristics. The method of manufacturing the semiconductor substrate including forming at least one floating body pattern by etching a bulk substrate, separating the bulk substrate into a substrate region and a floating body region by etching a lower middle portion of the floating body pattern, and filling an insulating material between the floating body region and the substrate region. | 05-26-2011 |
20110193940 | 3D CMOS Image Sensors, Sensor Systems Including the Same - A three-dimensional (3D) CMOS image sensor (CIS) that sufficiently absorbs incident infrared-rays (IRs) and includes an infrared-ray (IR) receiving unit formed in a thin epitaxial film, thereby being easily manufactured using a conventional CIS process, a sensor system including the 3D CIS, and a method of manufacturing the 3D CIS, the 3D CIS including an IR receiving part absorbing IRs incident thereto by repetitive reflection to produce electron-hole pairs (EHPs); and an electrode part formed on the IR receiving part and collecting electrons produced by applying a predetermined voltage thereto. | 08-11-2011 |
20120161277 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE MANUFACTURING METHODS - Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure. | 06-28-2012 |
20120224028 | METHOD OF FABRICATING MICROLENS, AND DEPTH SENSOR INCLUDING MICROLENS - A method of fabricating a microlens includes forming layer of photoresist on a substrate, patterning the layer of photoresist, and then reflowing the photoresist pattern. The layer of photoresist is formed by coating the substrate with liquid photoresist whose viscosity is 150 to 250 cp. A depth sensor includes a substrate and photoelectric conversion elements at an upper portion of the substrate, a metal wiring section disposed on the substrate, an array of the microlenses for focusing incident light as beams onto the photoelectric conversion elements and which beams avoid the wirings of the metal wiring section. The depths sensor also includes a layer presenting a flat upper surface on which the microlenses are formed. The layer may be a dedicated planarization layer or an IR filter, interposed between the microlenses and the metal wiring section. | 09-06-2012 |
20120268566 | THREE-DIMENSIONAL COLOR IMAGE SENSORS HAVING SPACED-APART MULTI-PIXEL COLOR REGIONS THEREIN - A three-dimensional color image sensor includes color pixels and depth pixels therein. A semiconductor substrate is provided with a depth region therein, which extends adjacent a surface of the semiconductor substrate. A two-dimensional array of spaced-apart color regions are provided within the depth region. Each of the color regions includes a plurality of different color pixels therein (e.g., red, blue and green pixels) and each of the color pixels within each of the spaced-apart color regions are spaced-apart from all other color pixels within other color regions. | 10-25-2012 |
20130010072 | SENSOR, DATA PROCESSING SYSTEM, AND OPERATING METHOD - An image sensor includes a unit pixel including a plurality of color pixels with a depth pixel. A first signal line group of first signal lines is used to supply first control signals that control operation of the plurality of color pixels, and a separate second signal line group of second signal lines is used to supply second control signals that control operation of the depth pixel. | 01-10-2013 |
20130161727 | NON-VOLATILE MEMORY DEVICE HAVING STACKED STRUCTURE, AND MEMORY CARD AND ELECTRONIC SYSTEM INCLUDING THE SAME - Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set. | 06-27-2013 |
20140015932 | 3DIMENSION IMAGE SENSOR AND SYSTEM INCLUDING THE SAME - A 3D image sensor includes a first color filter configured to pass wavelengths of a first region of visible light and wavelengths of infrared light; a second color filter configured to pass wavelengths of a second region of visible light and the wavelengths of infrared light; and an infrared sensor configured to detect the wavelengths of infrared light passed through the first color filter. | 01-16-2014 |
20140111423 | MOBILE SYSTEMS INCLUDING IMAGE SENSORS, METHODS OF OPERATING IMAGE SENSORS, AND METHODS OF OPERATING MOBILE SYSTEMS - A mobile system may comprise a three-dimensional (3D) image sensor on a first surface of the mobile system configured to perform a first sensing to detect proximity of a subject and a second sensing to recognize a gesture of the subject by acquiring distance information for the subject; and/or a display device on the first surface of the mobile system to display results of the first sensing and the second sensing. A mobile system may comprise a light source unit; a plurality of depth pixels; and/or a plurality of color pixels. The light source unit, the plurality of depth pixels, or the plurality of color pixels may be activated based on an operation mode of the mobile system. | 04-24-2014 |
20150069244 | UNIT PIXELS, DEPTH SENSORS AND THREE-DIMENSIONAL IMAGE SENSORS INCLUDING THE SAME - A unit pixel of a depth sensor includes a light-receiver configured to perform photoelectric conversion of an incident light to output an electrical signal and at least two sensors adjacent to the light-receiver to receive the electrical signal from the light-receiver such that a line connecting the sensors forms an angle greater than zero degrees with respect to a first line, the first line passing through a center of the light-receiver in a horizontal direction. | 03-12-2015 |