Patent application number | Description | Published |
20110185114 | SYSTEM AND METHOD FOR READ-WHILE-WRITE WITH NAND MEMORY DEVICE - System, method, and program to perform simultaneous read and write operations in a NAND-type memory device, including: assigning a first partition in a NAND-type memory device, wherein the first partition is configured to perform read operations on high priority read content; assigning a second partition in the NAND-type memory device, wherein the second partition is configured to perform read operations and write operations, wherein the read operations are performed on non-high priority read content; and controlling the first partition and second partition to operate in a simultaneous manner. | 07-28-2011 |
20120278532 | DYNAMICALLY CONFIGURABLE EMBEDDED FLASH MEMORY FOR ELECTRONIC DEVICES - Lifespan of embedded flash memory in an electronic device may be extended and efficient use of the MLC capabilities of the memory may be made by implementing an enhanced partition that stores content that is dynamically adjusted according to the memory usage of the device. The enhanced partition may be used to store data that has a relatively high frequency of updating as measured, for example, by write operations to corresponding memory addresses. In one embodiment, the size of the enhanced partition also may be adjusted in accordance with memory usage, such as basing the size of the enhanced partition on the frequently updated addresses. | 11-01-2012 |
20120324251 | OPTIMIZED HIBERNATE MODE FOR WIRELESS DEVICE - A system and method for reducing in boot time in an electronic device. In one embodiment, a command to power off the electronic device is received. An amount of information stored in at least one of the plurality of memory banks of RAM containing data is calculated. A determination is made as to whether the RAM has sufficient storage space to store compacted data and also form a RAM disk in a portion of the RAM, wherein the step of determining is based at least in part on the amount of information calculated. A RAM disk is initiated in an available memory bank of RAM. The RAM is compacted and a hibernate command is executed wherein the RAM disk is a target for storing the compacted RAM. Power is maintained to memory banks that form the RAM disk and the processor of the portable communication device is set to a power collapse mode. | 12-20-2012 |
20130219111 | SYSTEM AND METHOD FOR READ-WHILE-WRITE WITH NAND MEMORY DEVICE - System, method, and program to perform simultaneous read and write operations in a NAND-type memory device, including: assigning a first partition in a NAND-type memory device, wherein the first partition is configured to perform read operations on high priority read content; assigning a second partition in the NAND-type memory device, wherein the second partition is configured to perform read operations and write operations, wherein the read operations are performed on non-high priority read content; and controlling the first partition and second partition to operate in a simultaneous manner. | 08-22-2013 |
Patent application number | Description | Published |
20090100417 | Processor Controlled Device, in Particular Electronic Communication and/or Multimedia Device with Different Operation Modes - An electronic communication and/or multimedia device comprises a central processing unit controlling the operation of said device, wherein in a standard mode the operation of the device is carried out on the basis of data stored in the first memory said device. In a reduced mode of said device, a part of the data stored in said first memory is copied into second memory wherein the operation of said device in said reduced mode is carried out only on the basis of the data contained in said second memory. Said reduced mode might be used for updating the software of the device while still providing a basis functionality. | 04-16-2009 |
20110099313 | SYSTEM AND METHOD FOR CONTROLLING INTERRUPTION OF A PROCESS IN ELECTRONIC EQUIPMENT BASED ON PRIORITY OF THE PROCESS, AND PROGRAM - System, method, and program to determine whether to interrupt a process, e.g., a write function, to carry out another process, e.g., a high priority read function, in a device that uses memory devices, e.g., eMMC devices, that use a single channel to carry out two different processes, e.g., write and read processes. | 04-28-2011 |
20110099327 | SYSTEM AND METHOD FOR LAUNCHING AN APPLICATION PROGRAMMING UTILIZING A HYBRID VERSION OF DEMAND PAGING - A system and method for launching a computer application program stored in a nonvolatile medium, wherein by reusing a page load scheme from a standard demand page based launch. The system and method includes launching a computer application program one or more times using demand paging to load memory pages of the nonvolatile medium associated with the computer application into a volatile memory for execution of the computer application program. Memory address information corresponding to the pages of the nonvolatile medium corresponding to portions of the computer application program accessed during use of the computer application program are stored in a launch record. The computer application program is launched using the address information stored in the launch record to read nonvolatile medium addresses stored in the launch record in a single or consecutive read step. | 04-28-2011 |
20120307458 | MEMORY DEVICE AND RECEPTACLE FOR ELECTRONIC DEVICES - A random access memory (RAM) memory module has a compact form factor and is removable from a corresponding socket assembly to allow easy replacement of the memory module or reconfiguration of the memory module during development of an electronic device that includes the memory module. | 12-06-2012 |
Patent application number | Description | Published |
20110134933 | CLASSES OF SERVICE FOR NETWORK ON CHIPS - A method includes a local switch receiving a first set of upstream packets and a first set of local packets, each assigned a first class of service. The local switch inserts, according to a first insertion rate, a local packet between subsets of the first set of upstream packets to obtain an ordered set of first class packets. The local switch also receives a second set of upstream packets and a second set of local packets, each assigned a second class. The local switch inserts, according to a second insertion rate, a local packet between subsets of the second set of upstream packets to obtain an ordered set of second class packets. The method includes for each timeslot, selecting a class, and forwarding a packet from the selected class of service to a downstream switch. The switches are interconnected in a daisy chain topology on a single chip. | 06-09-2011 |
20110167191 | ARCHITECTURE FOR AN OUTPUT BUFFERED SWITCH WITH INPUT GROUPS - Embodiments of the present invention provide a system that transfers data between the components in the computer system through a switch. In these embodiments, the switch includes multiple switch chips which are coupled together and are configured to collectively function as a switch. During operation, each switch chip, receives cells from the subset of the set of inputs and selectively transfers each of the cells to at least one output of the subset of the set of outputs coupled to the switch chip or of the subset of the set of outputs coupled to the other switch chips. | 07-07-2011 |
20120170459 | SIMPLE LOW-JITTER SCHEDULER - A method for managing packets, including identifying a first packet source having a first weight and second packet source having a second weight, where the first weight exceeds the second weight; assembling a first regular subsequence of packets using a first packet from the second packet source and a first set of packets from the first packet source having a cardinality equal to a first weight ratio; assembling a first augmented subsequence of packets using a second packet from the second packet source and a second set of packets from the first packet source having a cardinality equal to the first weight ratio plus one; and forwarding a first sequence of packets including a first set of regular subsequences, which includes the first regular subsequence, and a first set of augmented subsequences, which includes the first augmented subsequence and has a cardinality based on the first augmented subsequence factor. | 07-05-2012 |
Patent application number | Description | Published |
20080314447 | Single P-N Junction Tandem Photovoltaic Device - A single P-N junction solar cell is provided having two depletion regions for charge separation while allowing the electrons and holes to recombine such that the voltages associated with both depletion regions of the solar cell will add together. The single p-n junction solar cell includes an alloy of either InGaN or InAlN formed on one side of the P-N junction with Si formed on the other side in order to produce characteristics of a two junction (2J) tandem solar cell through only a single P-N junction. A single P-N junction solar cell having tandem solar cell characteristics will achieve power conversion efficiencies exceeding 30%. | 12-25-2008 |
20090173373 | Group III-Nitride Solar Cell with Graded Compositions - A compositionally graded Group III-nitride alloy is provided for use in a solar cell. In one or more embodiment, an alloy of either InGaN or InAlN formed in which the In composition is graded between two areas of the alloy. The compositionally graded Group III-nitride alloy can be utilized in a variety of types of solar cell configurations, including a single P-N junction solar cell having tandem solar cell characteristics, a multijunction tandem solar cell, a tandem solar cell having a low resistance tunnel junction and other solar cell configurations. The compositionally graded Group III-nitride alloy possesses direct band gaps having a very large tuning range, for example extending from about 0.7 to 3.4 eV for InGaN and from about 0.7 to 6.2 eV for InAlN. | 07-09-2009 |
20100095998 | LOW RESISTANCE TUNNEL JUNCTIONS FOR HIGH EFFICIENCY TANDEN SOLAR CELLS - A semiconductor structure comprises a first photovoltaic cell comprising a first material, and a second photovoltaic cell comprising a second material and connected in series to the first photovoltaic cell. The conduction band edge of the first material adjacent the second material is at most 0.1 eV higher than a valence band edge of the second material adjacent the material. Preferably, the first material of the first photovoltaic cell comprises ln].χAlχN or lnt_yGayN and the second material of the second photovoltaic cell comprises silicon or germanium. Alternatively, the first material of the first photovoltaic cell comprises InAs or InAsSb and the second material of the second photovoltaic cell comprises GaSb or GaAsSb. | 04-22-2010 |
20100175751 | Dilute Group III-V Nitride Intermediate Band Solar Cells with Contact Blocking Layers - An intermediate band solar cell (IBSC) is provided including a p-n junction based on dilute III-V nitride materials and a pair of contact blocking layers positioned on opposite surfaces of the p-n junction for electrically isolating the intermediate band of the p-n junction by blocking the charge transport in the intermediate band without affecting the electron and hole collection efficiency of the p-n junction, thereby increasing open circuit voltage (V | 07-15-2010 |
20110005590 | Tandem Photoelectrochemical Cell for Water Dissociation - A tandem photoelectrochemical (PEC) cell including a nitride PEC semiconductor connected in series with a current matched photovoltaic (PV) Si solar cell that provides an internal biasing voltage. A low resistance tunnel junction is formed between the PEC semiconductor and PV cell. The tandem PEC cell is placed together with a counter electrode in contact with an aqueous solution, such that, when exposed to solar radiation, the PEC semiconductor utilizes high energy photons to split water while the PV cell utilizes low energy photons to bias the tandem PEC cell to eliminate the barrier between Fermi energy and redox potentials, thereby initiating the spontaneous dissociation of water in the aqueous solution into hydrogen and oxygen. The conduction band edge (CBE) for n-type PEC semiconductor is located in the vicinity of the Fermi stabilization energy to reduce the barriers for the charge transfer between the PEC semiconductor and the aqueous solution. | 01-13-2011 |
20120031491 | Single P-N Junction Tandem Photovoltaic Device - A single P-N junction solar cell is provided having two depletion regions for charge separation while allowing the electrons and holes to recombine such that the voltages associated with both depletion regions of the solar cell will add together. The single p-n junction solar cell includes an alloy of either InGaN or InAlN formed on one side of the P-N junction with Si formed on the other side in order to produce characteristics of a two junction (2J) tandem solar cell through only a single P-N junction. A single P-N junction solar cell having tandem solar cell characteristics will achieve power conversion efficiencies exceeding 30%. | 02-09-2012 |
20120125417 | Photovoltaic Device With Three Dimensional Charge Separation and Collection - A photovoltaic device having three dimensional (3D) charge separation and collection, where charge separation occurs in 3D depletion regions formed between a p-type doped group III-nitride material in the photovoltaic device and intrinsic structural imperfections extending through the material. The p-type group III-nitride alloy is compositionally graded to straddle the Fermi level pinning by the intrinsic structural imperfections in the material at different locations in the group III-nitride alloy. A field close to the surfaces of the intrinsic defects separates photoexcited electron-hole pairs and drives the separated electrons to accumulate at the surfaces of the intrinsic defects. The intrinsic defects function as n-type conductors and transport the accumulated electrons to the material surface for collection. The compositional grading also creates a potential that drives the accumulated separated electrons toward an n-type group III-nitride layer for collection. The p-type group III-nitride alloy may comprise an alloy of InGaN, InAlN or InGaAlN. | 05-24-2012 |
20120273037 | DILUTE GROUP III-V NITRIDE INTERMEDIATE BAND SOLAR CELLS WITH CONTACT BLOCKING LAYERS - An intermediate band solar cell (IBSC) is provided including a p-n junction based on dilute III-V nitride materials and a pair of contact blocking layers positioned on opposite surfaces of the p-n junction for electrically isolating the intermediate band of the p-n junction by blocking the charge transport in the intermediate band without affecting the electron and hole collection efficiency of the p-n junction, thereby increasing open circuit voltage (V | 11-01-2012 |
20130026484 | Multi-Color Light Emitting Devices with Compositionally Graded Cladding Group III-Nitride Layers Grown on Substrates - A light emitting device includes a substrate, multiple n-type layers, and multiple p-type layers. The n-type layers and the p-type layers each include a group III nitride alloy. At least one of the n-type layers is a compositionally graded n-type group III nitride, and at least one of the p-type layers is a compositionally graded p-type group III nitride. A first ohmic contact for injecting current is formed on the substrate, and a second ohmic contact is formed on a surface of at least one of the p-type layers. Utilizing the disclosed structure and methods, a device capable of emitting light over a wide spectrum may be made without the use of phosphor materials. | 01-31-2013 |
20130074901 | COMPOSITIONALLY GRADED DILUTE GROUP III-V NITRIDE CELL WITH BLOCKING LAYERS FOR MULTIJUNCTION SOLAR CELL - A dilute Group III-V nitride solar cell is provided for use in a multijunction solar cell having a p-n junction formed by p-type and n-type layers of dilute Group III-V nitride material, such as GaNAs. Blocking layers of a group III-V ternary alloy are formed on opposing surfaces of the p-n junction to improve the electron and hole collection efficiency of the p-n junction by preventing the flow of electrons and holes, respectively, into the adjacent layers of the multijunction solar cell in certain directions. The III-V nitride solar cell is current matched to other solar cells of the multijunction solar cell. The III-V nitride solar cell may possess a bandgap of approximately 1.0 eV to serve as one junction of the multijunction solar cell. The p-type and n-type layers may further have compositionally graded nitrogen concentrations to provide an electric field for more efficient charge collection. | 03-28-2013 |
20130074912 | BAND STRUCTURE ENGINEERING FOR IMPROVED EFFICIENCY OF CDTE BASED PHOTOVOLTAICS - Disclosed is a solar cell or component thereof that includes a p-type thin film solar light absorbing layer having one or more compositions of group II-VI alloys described as CdTe | 03-28-2013 |
20130126892 | P-Type Amorphous GaNAs Alloy as Low Resistant Ohmic Contact to P-Type Group III-Nitride Semiconductors - A new composition of matter is described, amorphous GaN | 05-23-2013 |
20140261690 | INTERMEDIATE BAND SOLAR CELLS WITH DILUTE GROUP III-V NITRIDES - A single junction solar cell may be manufactured with a material having multiple bands. That is, a single semiconductor with several absorption edges that absorb photons from different parts of the solar spectrum may be constructed. The different absorption edges may be created by splitting a conduction band of the solar cell material into multiple intermediate sub-bands. The solar cell may include a photovoltaic material deposited on a substrate, in which the photovoltaic material is a III-V semiconductor alloy, such as AlGaNAs, AlGaAsNSb, or AlInGaNAsBi. | 09-18-2014 |
Patent application number | Description | Published |
20090206290 | LOW POWER ACTUATOR AND VALVE-ACTUATOR COMBINATION - Actuators and valve-actuator combinations are disclosed which require low power for actuation, and which are particularly suitable for use to control a valve associated with a pipeline. Such an actuator ( | 08-20-2009 |
20100327653 | AIR BRAKING SYSTEM - An air braking unit for use in an air braking system. The air braking unit is arranged to be positioned, in use, at a vehicle wheel, and comprises an inlet for receiving, in use, compressed air from a central source. At least one first valve is arranged to selectively allow compressed air from the inlet to enter a wheel brake chamber in use. At least one second valve is arranged to selectively allow air from the brake chamber to be released via an outlet to the atmosphere in use and control means controls the first and second valves to operate to selectively control the air pressure in the brake chamber in use. | 12-30-2010 |
20110083855 | Gas Injection Control Devices and Methods of Operation Thereof - Gas injection control devices are provided, particularly for deployment in a well-bore to control injection of a gas into a tube or pipe to lift a liquid up the tube, such as crude oil for example. A gas control device is described which comprises a housing, and at least two control valve arrangements within the housing. Each arrangement has an inlet for receiving gas from a pressurized supply, an outlet for supplying pressurized gas for injection into the tube, an inlet valve in a fluid path between the inlet and outlet, and an actuator associated with the inlet valve. Each actuator is independently controllable to switch the respective inlet valve between its open and closed configurations. This allows the gas injection to be switched on and off, and facilitates control of the injection gas flow rate. | 04-14-2011 |
20110248804 | Multistable Electromagnetic Actuators - A multistable electromagnetic actuator is provided which addresses a need for a more robust, reliable and energy efficient actuation device. It comprises an armature ( | 10-13-2011 |