Patent application number | Description | Published |
20110020930 | Enrichment of Stem Cells from Adult Tissues - Subjecting a heterogeneous cell population (one with both stem cells and non-stem cells) to extreme stress selectively eliminated the non-stem cells and resulted in the enrichment of stem cells in the population. The stress can take many forms, including without limitation, cell toxins, high temperature, high salt, and low oxygen (hypoxic) conditions. The number of stem cells remaining after stress were increased, and showed increased expression of traditional stem cell markers. The stem cells were shown to be capable of proliferation and differentiation into multiple types of cells. This method allows purification of stem cells from adult heterogeneous cell populations on a large scale basis without requirement of expensive equipment, and without requiring the presence of cell surface markers. Stem cells produced by the above method can be used for clinical applications, including tissue engineering. | 01-27-2011 |
20130295670 | Enrichment of Stem Cells from Adult Tissues - Subjecting a heterogeneous cell population (one with both stem cells and non-stem cells) to extreme stress selectively eliminated the non-stem cells and resulted in the enrichment of stem cells in the population. The stress can take many forms, including without limitation, cell toxins, high temperature, high salt, and low oxygen (hypoxic) conditions. The number of stem cells remaining after stress were increased, and showed increased expression of traditional stem cell markers. The stem cells were shown to be capable of proliferation and differentiation into multiple types of cells. This method allows purification of stem cells from adult heterogeneous cell populations on a large scale basis without requirement of expensive equipment, and without requiring the presence of cell surface markers. Stem cells produced by the above method can be used for clinical applications, including tissue engineering. | 11-07-2013 |
Patent application number | Description | Published |
20080303027 | Semiconductor Device Made by the Method of Producing Hybrid Orientnation (100) Strained Silicon with (110) Silicon - There is provided a method of manufacturing a semiconductor device. In one aspect, the method includes providing a strained silicon layer having a crystal orientation located over a semiconductor substrate having a different crystal orientation. A mask is placed over a portion of the strained silicon layer to leave an exposed portion of the strained silicon layer. The exposed portion of the strained silicon layer is amorphized and re-crystallized to a crystal structure having an orientation the same as the semiconductor substrate. | 12-11-2008 |
20080308847 | METHOD OF MAKING (100) NMOS AND (110) PMOS SIDEWALL SURFACE ON THE SAME FIN ORIENTATION FOR MULTIPLE GATE MOSFET WITH DSB SUBSTRATE - A method of forming an integrated circuit device that includes a plurality of MuGFETs is disclosed. A PMOS fin of a MuGFET is formed on a substrate. The PMOS fin includes a channel of a first surface of a first crystal orientation. A NMOS fin of another MuGFET is formed on the substrate. The NMOS fin includes a channel on the substrate at one of 0° and 90° to the PMOS fin and includes a second surface of a second crystal orientation. | 12-18-2008 |
20090057816 | METHOD TO REDUCE RESIDUAL STI CORNER DEFECTS GENERATED DURING SPE IN THE FABRICATION OF NANO-SCALE CMOS TRANSISTORS USING DSB SUBSTRATE AND HOT TECHNOLOGY - A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing. | 03-05-2009 |
20100304547 | REDUCTION OF STI CORNER DEFECTS DURING SPE IN SEMICONDCUTOR DEVICE FABRICATION USING DSB SUBSTRATE AND HOT TECHNOLOGY - A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing. | 12-02-2010 |
20110057289 | Ultrashallow Emitter Formation Using ALD and High Temperature Short Time Annealing - An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·10 | 03-10-2011 |
20110151651 | METHOD FOR FORMING INTEGRATED CIRCUITS WITH ALIGNED (100) NMOS AND (110) PMOS FINFET SIDEWALL CHANNELS - A method of forming an integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations. | 06-23-2011 |
20120175710 | INTEGRATED CIRCUITS WITH ALIGNED (100) NMOS AND (110) PMOS FINFET SIDEWALL CHANNELS - An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having ( | 07-12-2012 |
20130029471 | REDUCTION OF STI CORNER DEFECTS DURING SPE IN SEMICONDUCTOR DEVICE FABRICATION USING DSB SUBSTRATE AND HOT TECHNOLOGY - A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing. | 01-31-2013 |
20130062720 | EXTENDED AREA COVER PLATE FOR INTEGRATED INFRARED SENSOR - An integrated circuit chip includes a window cover over etchant holes in a dielectric layer and over a cavity in the substrate of said integrated circuit chip. The window cover extends at least 400 microns beyond the edge of the cavity. An integrated sensor chip with a sensor cover which extends at least 400 microns beyond the edges of a cavity. A method of forming an integrated sensor chip with a sensor cover which extends at least 400 microns beyond the edge of a cavity. | 03-14-2013 |
20140035057 | INTEGRATED CIRCUITS WITH ALIGNED (100) NMOS AND (110) PMOS FINFET SIDEWALL CHANNELS - An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations. | 02-06-2014 |
20140045321 | ACCELERATED FURNACE RAMP RATES FOR REDUCED SLIP - A method for fabricating an integrated circuit (IC) includes initial oxidizing of a semiconductor surface of a substrate. The substrate is heated after the initial oxidizing using a plurality of furnace processing steps which each include a peak processing temperature between 800° C. and 1300° C. The furnace processing steps include at least one accelerated processing step having an accelerated ramp portion in a temperature range between 800° C. and 1250° C. providing an accelerated ramp-up rate and/or an |accelerated ramp-down rate| of at least (≧) 5.5° C./min. | 02-13-2014 |
20140329370 | LAYER TRANSFER OF SILICON ONTO III-NITRIDE MATERIAL FOR HETEROGENOUS INTEGRATION - An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first orientation. A second silicon substrate with a second, different, orientation has a release layer between a silicon device film and a carrier wafer. The silicon device film is attached to the III-N semiconductor material while the silicon device film is connected to the carrier wafer through the release layer. The carrier wafer is subsequently removed from the silicon device film. A first plurality of components is formed in and/or on the silicon device film. A second plurality of components is formed in and/or on III-N semiconductor material in the exposed region. In an alternate process, a dielectric interlayer may be disposed between the silicon device film and the III-N semiconductor material in the integrated silicon and III-N semiconductor device. | 11-06-2014 |
20140339678 | Ultrashallow Emitter Formation Using ALD and High Temperature Short Time Annealing - An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·10 | 11-20-2014 |
20150014789 | INTEGRATED CIRCUITS WITH ALIGNED (100) NMOS AND (110) PMOS FINFET SIDEWALL CHANNELS - An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orienations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations. | 01-15-2015 |
20150118861 | CZOCHRALSKI SUBSTRATES HAVING REDUCED OXYGEN DONORS - A method of semiconductor fabrication includes providing an unpatterned lightly doped Czochralski bulk silicon substrate (LDCBS substrate) having a concentration of oxygen atoms of at least (≧) 10 | 04-30-2015 |
20150187597 | METHOD TO IMPROVE SLIP RESISTANCE OF SILICON WAFERS - By controlling the concentration and size of bulk micro defects (BMD) during the manufacture of an integrated circuit slip and associated yield loss due to slip may be eliminated. A process for eliminating slip that is customized to an integrated circuit (IC) manufacturing flow is disclosed. The process is adapted to the oxygen content of the starting material and to the thermal budget of an IC manufacturing flow and generates a sufficient concentration of BMDs of a size that is optimized to getter microcracks thereby eliminating slip. Slip is eliminated in unpatterned wafers and in wafers containing shallow trench isolation and deep trench isolation using a BMD nucleation anneal and a BMD growth anneal. | 07-02-2015 |
20150187770 | HIGH MOBILITY TRANSISTORS - An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins. | 07-02-2015 |
20150187773 | HIGH MOBILITY TRANSISTORS - An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately. | 07-02-2015 |
20150243494 | MECHANICALLY ROBUST SILICON SUBSTRATE HAVING GROUP IIIA-N EPITAXIAL LAYER THEREON - A method of forming an epitaxial article includes growing a crystal of elemental silicon having a minimum boron doping level of 3.2×10 | 08-27-2015 |
20150295556 | TEMPERATURE COMPENSATED BULK ACOUSTIC WAVE RESONATOR WITH A HIGH COUPLING COEFFICIENT - The dominant frequency of a solidly mounted resonator ( | 10-15-2015 |