Patent application number | Description | Published |
20150026756 | COORDINATION OF MULTIPATH TRAFFIC - In one implementation, traffic in a mobile network is directed across multiple paths to a single cloud server or security server (e.g., a security as a service). The mobile device detects a cloud connector through a primary connection based on an attachment or connection via a first interface of a mobile device. The mobile device sends a request to the cloud connector for an identification of a cloud security server associated with the cloud connector. After receiving the identification of the cloud security server, the mobile device directs one or more subsequent data flows or subflows for a second interface or another interface of the mobile device to the cloud server or security server. The second data flow and the second interface are associated with another network that is external to the enterprise network and trusted network connection or not associated with the enterprise network and the trusted network connection. | 01-22-2015 |
20150026757 | Web Caching with Security as a Service - In one implementation, Web-Cache deployed in the Enterprise premises and cloud-based SecaaS are combined such that similar identity-based polices are enforced on both the SecaaS and content delivered from the Web-Cache. This identity-based policy implementation outside the network using SecaaS and within the network for web-cached content provides consistent identity-based security while still providing content to end-users with high performance. Content inspected and/or modified by SecaaS may be cached in the enterprise premises so that requests for content from an origin server decreases, freeing Internet bandwidth and reducing access time. Local caching of streaming content may decrease latency while local implementation of identity-based policy continues to limit the streamed content as appropriate. Local implementation of identity-based policy may reduce the load on SecaaS. Rather than using content delivery networks provided by a service provider for web-content, a cache server within the enterprise is used. | 01-22-2015 |
20150113588 | Firewall Limiting with Third-Party Traffic Classification - A PCP-aware firewall or other firewall validating a media session using third-party authorization receives more information than just the results of cryptographic token validation. The intent for each media stream of a media session is received from the Authorization Server. The intent may be used to compare to the received traffic of the media session. If the traffic is different than the intended traffic, then the exception to permit the firewall may be closed. | 04-23-2015 |
20150149657 | Path Optimization for Adaptive Streaming - In one implementation, downloading of streaming content using a security as a service (SecaaS) system is more efficient because portions of the streaming content may not be inspected by the SecaaS. A first request to download content from a content provider is received, and a connection is initiated with a security provider, which inspects the first chunk of the content and generates a routing instruction based on the inspection of the first chunk of content. Based on the routing instructions and the inspection of the first chunk, a request for a second chunk of the streaming content is addressed to the content provider. The second chunk of the streaming content, circumvents the SecaaS system. | 05-28-2015 |
Patent application number | Description | Published |
20080248669 | HIGH VOLTAGE ELECTRICAL CONNECTORS - The present invention is directed to a connector housing for high voltage wires, either single ended or double ended with an integrated connector. Other features of the present invention include integration of a deep recessed high voltage connector contact for an arc and leakage resistant high voltage connection point, use of a female socket pin embedded at the base of the connector. The socket pin is co-molded into the connection end of the body, or it is co-molded or press fitted into a hole at the end of the connector housing. | 10-09-2008 |
20080303505 | Self Tuning High Voltage Power Supply - A self tuning high voltage power supply comprising a signal generator that emits a variable frequency signal, an amplifier that receives the variable frequency signal and emits an amplified variable frequency signal, and a transformer that receives and steps up the amplified variable frequency signal, creating an output voltage that corresponds to a desired voltage. A measuring unit measures the power consumed by the amplifier and provides a reading to a processing unit, which receives such reading and tunes the signal generator to emit a variable frequency signal that is at the frequency of resonance of the transformer. This causes the transformer to operate at conditions of resonance and to substantially eliminate power losses due to stray capacitance and stray inductance. As a consequence, the self tuning high voltage power supply can deliver the desired voltage with minimum power consumption. | 12-11-2008 |
20100302746 | HIGH VOLTAGE RECESSED CONNECTOR CONTACT - A process relating to a one step low pressure injection molding method of encapsulating high voltage circuitry while incorporating a unique recessed high voltage connector contact means within the injection molding material, greatly reducing the component size, while increasing the capabilities of this type of circuitry. The process reduces the manufacturing time and maintains a clean sealed contact point for repeated usage by the means of a conductive rubber slug. An additional advantage is by creating cavities through the circuit board; axially leaded high voltage components may be conveniently mounted without additional assembly components while being fully encapsulated. | 12-02-2010 |
20100314792 | LOW PRESSURE MOLDING ENCAPSULATION OF HIGH VOLTAGE CIRCUITRY - A process relating to a one step low pressure injection molding method of encapsulating high voltage circuitry while incorporating a unique recessed high voltage connector contact means within the injection molding material, greatly reducing the component size, while increasing the capabilities of this type of circuitry. The process reduces the manufacturing time and maintains a clean sealed contact point for repeated usage by the means of a conductive rubber slug. An additional advantage is by creating cavities through the circuit board; axially leaded high voltage components may be conveniently mounted without additional assembly components while being fully encapsulated. | 12-16-2010 |
20100321967 | REGULATED OUTPUT CURRENT AND SLOPE CONTROL - The present invention is directed to current mode output control with a current mode (CM) region of the high voltage output curve (VI) slope controlled by component selection and arrangement in the construction of high voltage power supplies. The controlled CM current slope output, the tapped multiplier feedback network, and the subsequent output voltage correction network, yields a power supply with the desired VM and CM output characteristics that is significantly less expensive to construct and more efficient than a power supply built using conventional construction techniques. | 12-23-2010 |
20120017436 | Selective encapsulation of electronic components - A method for the selective encapsulation of electronic components on a printed circuit board comprising, in one embodiment, the steps of delivering the printed circuit board to an encapsulating nest at room temperature; damming the target areas with a dam resin having a latent curing agent and deposited in the shape of walls of predetermined heights, according to the desired fill heights; dispensing a fill resin to fill the dammed areas; and curing the dam and fill resins for a suitable amount of time. In a different embodiment, the invention comprises the additional steps of laying resin beads, each in a position corresponding to the footprint of each target component; and of positioning the target components over the beads and soldering the components. | 01-26-2012 |
Patent application number | Description | Published |
20140063901 | MEMORY DEVICES, CIRCUITS AND, METHODS THAT APPLY DIFFERENT ELECTRICAL CONDITIONS IN ACCESS OPERATIONS - A memory device can include a plurality of memory elements programmable between different impedance states; and circuits configured to apply first electrical conditions to one group of memory elements and second electrical conditions, different from the first electrical conditions, to another group of memory elements to vary a speed of an access operation to the different groups of memory elements. | 03-06-2014 |
20140063902 | MEMORY DEVICES, CIRCUITS AND, METHODS THAT APPLY DIFFERENT ELECTRICAL CONDITIONS IN ACCESS OPERATIONS - A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block. | 03-06-2014 |
20140089560 | MEMORY DEVICES AND METHODS HAVING WRITE DATA PERMUTATION FOR CELL WEAR REDUCTION - A memory system can include a plurality of memory elements each comprising a memory layer having at least one layer programmable between at least two different impedance states; a data input configured to receive multi-bit write data values; and a permutation circuit coupled between the memory elements and the data input, and configured to repeatedly permute the multi-bit write data values prior to writing such data values into the memory elements. | 03-27-2014 |
20140149639 | CODING TECHNIQUES FOR REDUCING WRITE CYCLES FOR MEMORY - Structures and methods for encoding data to reduce write cycles in a semiconductor memory device are disclosed herein. In one embodiment, a method of writing data to a semiconductor memory device can include: (i) determining a number of significant bits for data to be written in the semiconductor memory device; (ii) determining a tag associated with the data to be written in the semiconductor memory device, where the tag is determined based on the determined number of significant bits; (iii) encoding the data when the tag has a first state, where the tag is configured to indicate data encoding that comprises using N bits of the encoded data to store M bits of the data, where M and N are both positive integers and N is greater than M; and (iv) writing the encoded data and the tag in the semiconductor memory device. | 05-29-2014 |
20140173154 | NETWORK INTERFACE WITH LOGGING - Structures and methods for improving logging in network structures are disclosed herein. In one embodiment, an apparatus can include: (i) a network interface card (NIC) configured to receive data, to transmit data, and to send data for logging; (ii) a memory log coupled to the NIC, where the memory log comprises non-volatile memory (NVM) configured to write the data sent for logging from the NIC; and (iii) where the data being sent for logging by the memory log occurs substantially simultaneously with the data being received by the NIC, and the data being transmitted from the NIC. | 06-19-2014 |
Patent application number | Description | Published |
20090072858 | HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUIT - A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system. | 03-19-2009 |
20090073967 | High-bandwidth interconnect network for an integrated circuit - A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits. | 03-19-2009 |
20090073970 | SYSTEM AND METHOD FOR PARSING FRAMES - A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit. | 03-19-2009 |
20100306429 | System and Method of Signal Processing Engines With Programmable Logic Fabric - A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits. | 12-02-2010 |
20100329262 | System and Method for Parsing Frames - A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit. | 12-30-2010 |
20110317720 | System and Method for Parsing Frames - A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit. | 12-29-2011 |