Patent application number | Description | Published |
20080235431 | Method Using a Master Node to Control I/O Fabric Configuration in a Multi-Host Environment - A method is directed to use of a master root node, in a distributed computer system provided with multiple root nodes, to control the configuration of routings through an I/O switched-fabric. One of the root nodes is designated as the master root node or PCI Configuration Manager (PCM), and is operable to carry out the configuration while each of the other root nodes remains in a quiescent or inactive state. In one useful embodiment pertaining to a system of the above type, that includes multiple root nodes, PCI switches, and PCI adapters available for sharing by different root nodes, a method is provided wherein the master root node is operated to configure routings through the PCI switches. Respective routings are configured between respective root nodes and the PCI adapters, wherein each of the configured routings corresponds to only one of the root nodes. A particular root node is enabled to access each of the PCI adapters that are included in any configured routing that corresponds to the particular root node. At the same time, the master root node writes into a particular root node only the configured routings that correspond to the particular root node. Thus, the particular root node is prevented from accessing an adapter that is not included in its corresponding routings. | 09-25-2008 |
20080235785 | Method, Apparatus, and Computer Program Product for Routing Packets Utilizing a Unique Identifier, Included within a Standard Address, that Identifies the Destination Host Computer System - A computer-implemented method, apparatus, and computer program product are disclosed in a data processing environment that includes host computer systems that are coupled to adapters utilizing a switched fabric for routing packets between the host computer systems and the adapters. A unique destination identifier is assigned to one of the host computer systems. A portion of a standard format packet destination address is selected. Within a particular packet, the portion is set equal to the unique identifier that is assigned to the host computer system. The particular packet is then routed through the fabric to the host computer system using the unique destination identifier. | 09-25-2008 |
20080270853 | Method of Routing I/O Adapter Error Messages in a Multi-Host Environment - A method and apparatus is provided for routing error messages in a distributed computer system comprising multiple root nodes, and further comprising one or more PCI switches and one or more I/O adapters, wherein each root node includes one or more system images. In one useful embodiment, a method is provided for routing I/O error messages to root nodes respectively associated with the errors contained in the messages. The method includes detecting occurrence of an error at a specified one of the adapters, wherein the error affects one of the system images, and generating an error message at the specified adapter. The method further comprises routing the error message from the specified adapter to the particular root node that includes the affected system image. The error message is then selectively processed at the particular root node, in order to identify the affected system image. Usefully, the step of routing the error message includes using a bus/device/function number associated with the error, together with a routing table located in one of the PCI switches, to route the error message to the correct root node and system image. | 10-30-2008 |
20080307116 | Routing Mechanism in PCI Multi-Host Topologies Using Destination ID Field - Method and system for address routing in a distributed computing system, such as a distributed computing system that uses PCI Express protocol to communicate over an I/O fabric. A destination identifier is provided to identify a physical or virtual host or end point. When a physical or virtual host or end point receives a PCI data packet it compares a list of source identifiers with destination identifiers to determine if a source identifier included in the transaction packet is associated with a destination identifier included in the transaction packet to determine if the transaction packet has a valid association. If the transaction packet has a valid association, it is routed to the target device. The present invention enables each host that attaches to PCI bridges or switches and shares a set of common PCI devices to have its own PCI 64-bit address space and enables the routing of PCI transaction packets between multiple hosts and adapters, through a PCI switched-fabric bus using a destination identifier. | 12-11-2008 |
20090100204 | Method, Apparatus, and Computer Usable Program Code for Migrating Virtual Adapters from Source Physical Adapters to Destination Physical Adapters - A computer-implemented method, apparatus, and computer usable program code are disclosed for migrating a virtual adapter from a source physical adapter to a destination physical adapter in a data processing system where multiple host computer systems share multiple adapters and communicate with those adapters through a PCI switched-fabric bus. The virtual adapter is first caused to stop processing transactions. All in-flight transactions that are associated with the virtual adapter are then captured. The configuration information that defines the virtual adapter is moved from the source physical adapter to the destination physical adapter. The in-flight transactions are then restored to their original locations on the destination virtual adapter. The virtual adapter is then restarted on the destination physical adapter such that the virtual adapter begins processing transactions. | 04-16-2009 |
20090119551 | Broadcast of Shared I/O Fabric Error Messages in a Multi-Host Environment to all Affected Root Nodes - A method, mechanism and computer usable medium is provided for distributing I/O fabric errors to the appropriate root nodes in a multi-root environment. The case where the I/O fabric is attached to more than one root node and where each root can potentially share with the other roots the I/O adapter (IOA) resources which are attached to the I/O is addressed. Additionally, a method, mechanism and computer usable medium is provided by which errors detected in an I/O fabric may be routed to all root nodes which may be affected by the error, while not being reported to the root nodes that will not be affected by those errors. In particular, distributed computing system which uses the PCI Express protocol to communicate over the I/O fabric is addressed. | 05-07-2009 |
20110239015 | Allocating Computing System Power Levels Responsive to Service Level Agreements - A computer program product for initiating a task in a computer system including executing a method that includes receiving a task and a status of the task relative to a target service level. A current power state of the processor is determined. Execution of the task is initiated on the processor in response to the status indicating that the task is meeting the target service level and to the current power state being a low power state. It is determined if the processor can be moved into a high power state, the determining performed if the task is not meeting the target service level and the current power state is the low power state. If the processor can be moved into the high power state then the processor is moved into the high power state and execution of the task is initiated on the processor. | 09-29-2011 |
20110239016 | Power Management in a Multi-Processor Computer System - Power management in a multi-processor computer system, including a computer program product for facilitating receiving a task for execution in a high power state, and determining a current power state of a processor in a multi-processor system, the system having a specified power limit. The task is dispatched to the processor if the current power state of the processor is the high power state. If the processor is not in the high power state, then it is determined if moving the processor into the high power state will cause the multi-processor system to exceed the specified power limit. The processor is moved into the high power state in response to determining that moving the processor into the high power state will not cause the multi-processor system to exceed the specified power limit. The task is dispatched to the processor in response to moving the processor into the high power state. | 09-29-2011 |
20140325098 | HIGH THROUGHPUT HARDWARE ACCELERATION USING PRE-STAGING BUFFERS - Embodiments relate to providing high throughput hardware acceleration. Aspects include initializing an accelerator control queue (ACQ) configured to provide location information on a plurality of pages of data identified as accelerator data. An originating location of each page of requested target data is determined. The originating location includes one of system memory and disk storage. Based on determining that the originating location is system memory, an entry is created in the ACQ mapping to a system memory source address for the target data. Based on determining that the originating location is disk storage, an entry is created in the ACQ mapping to a special pre-stage buffer source address of a special pre-stage buffer for the target data. Each page of the plurality of pages of target data is accessed by the accelerator from respective locations in said memory or said special pre-stage buffer, based on respective entries of the ACQ. | 10-30-2014 |