Patent application number | Description | Published |
20080223514 | SYSTEMS AND METHODS FOR ELECTRICAL CONTACTS TO ARRAYS OF VERTICALLY ALIGNED NANORODS - Systems and methods may provide electrical contacts to an array of substantially vertically aligned nanorods. The nanorod array may be fabricated on top of a conducting layer that serves as a bottom contact to the nanorods. A top metal contact may be applied to a plurality of nanorods of the nanorod array. The contacts may allow I/V (current/voltage) characteristics of the nanorods to be measured. | 09-18-2008 |
20090053845 | Method For Controlling The Structure And Surface Qualities Of A Thin Film And Product Produced Thereby - A system and method for providing improved surface quality following removal of a substrate and template layers from a semiconductor structure provides an improved surface quality for a layer (such as a quantum well heterostructure active region) prior to bonding a heat sink/conductive substrate to the structure. Following the physical removal of a sapphire substrate, a sacrificial coating such as a spin-coat polymer photoresist is applied to an exposed GaN surface. This sacrificial coating provides a planar surface, generally parallel to the planes of the interfaces of the underlying layers. The sacrificial coating and etching conditions are selected such that the etch rate of the sacrificial coating approximately matches the etch rate of GaN and the underlying layers, so that the physical surface profile during etching approximates the physical surface profile of the sacrificial coating prior to etching. Following etching, a substrate is bonded to the exposed surface which acts as a heat sink and may be conductive providing for backside electrical contact to the active region. | 02-26-2009 |
20090113685 | Methods to make piezoelectric ceramic thick film array and single elements and devices - A method of producing at least one piezoelectric element includes depositing a piezoelectric ceramic material onto a surface of a first substrate to form at least one piezoelectric element structure. Then an electrode is deposited on a surface of the at least one piezoelectric element structure. Next, the at least one piezoelectric element structure is bonded to a second substrate, the second substrate being conductive or having a conductive layer. The first substrate is then removed from the at least one piezoelectric element structure and a second side electrode is deposited on a second surface of the at least one piezoelectric element structure. A poling operation is performed to provide the at least one piezoelectric element structure with piezoelectric characteristics. | 05-07-2009 |
20090159940 | STRUCTURE AND METHOD FOR FLEXIBLE SENSOR ARRAY - A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array. | 06-25-2009 |
20090161409 | CHARGE MAPPING MEMORY ARRAY FORMED OF MATERIALS WITH MUTABLE ELECTRICAL CHARACTERISTICS - A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. | 06-25-2009 |
20090185018 | DIGITAL LITHOGRAPHY USING REAL TIME QUALITY CONTROL - A digital lithography system including a droplet source (printhead) for selectively ejecting liquid droplets of a phase-change masking material, and an imaging system for capturing (generating) image data representing printed features formed by the ejected liquid droplets. The system also includes a digital control system that detects defects in the printed features, for example, by comparing the image data with stored image data. The digital control system then modifies the printed feature to correct the defect, for example, by moving the printhead over the defect and causing the printhead to eject droplets onto the defect's location. In one embodiment, a single-printhead secondary printer operates in conjunction with a multi-printhead main printer to correct defects. | 07-23-2009 |
20090201325 | Method For The Printing Of Homogeneous Electronic Material With A Multi-Ejector Print Head - Printing systems are disclosed that produce homogenous, smooth edged printed patterns (such as integrated circuit (IC) patterns) by separating pattern layouts into discrete design layers having only parallel layout features. By printing each design layer in a printing direction aligned with the parallel layout features, the individual print solution droplets deposited onto the substrate do not dry before adjacent droplets are deposited. Therefore, printed patterns having accurate geometries and consistent electrical properties can be printed. | 08-13-2009 |
20090289333 | Annealing a Buffer Layer for Fabricating Electronic Devices on Compliant Substrates - A method of forming a thin-film layered electronic device over a flexible substrate comprises the steps of depositing a buffer layer over the flexible substrate, heating the substrate and buffer layer stack to a temperature at which plastic deformation of the buffer layer takes place, cooling the stack, then forming the thin-film electronic device over the plastically deformed buffer layer without further plastic deformation of the buffer layer. The heating and cooling to cause plastic deformation of the buffer layer is referred to as annealing. The thin-film electronic device is formed by a process according to which all steps are performed at a temperature below that at which further plastic deformation of the buffer layer occurs. In-process strain and runout are reduced, improving device yield on flexible substrates. An optional metal base layer may be formed over the buffer layer prior annealing. | 11-26-2009 |
20090294767 | Isolated Sensor Structures Such As For Flexible Substrates - A photosensor structure includes a pixel metal layer disposed in physical and electrical contact with a pixel thin film transistor and a lower sensor layer of a p-i-n photosensor. The pixel metal layer extends laterally to an extent less that the lower sensor layer such that an overhang region is defined below the lower sensor layer and the adjacent the lateral edge of the pixel metal layer. When the relatively thick intrinsic sensor layer is formed over the lower sensor layer, it attaches to the upper surface and, due to the presence of the overhang region, the lateral edge of the lower sensor layer, forming a discrete intrinsic sensor layer structure over the pixel which is physically isolated from adjacent corresponding structures. This isolation allows for thermal expansion and contraction during formation of the intrinsic sensor layer without cracking the intrinsic sensor layer structure. | 12-03-2009 |
20090294768 | SELF-ALIGNED THIN-FILM TRANSISTOR AND METHOD OF FORMING SAME - A method of manufacturing a thin-film transistor or like structure provides conductive “tails” below an overhang region formed by a top gate structure. The tails increase in thickness as they extend outward from a point under the overhang to the source and drain contacts. The tails provide a low resistance conduction path between the source and drain regions and the channel, with low parasitic capacitance. The thickness profile of the tails is controlled by the deposition of material over and on the lateral side surfaces of the gate structure. | 12-03-2009 |
20090298240 | SELF-ALIGNED THIN-FILM TRANSISTOR AND METHOD OF FORMING SAME - A method of manufacturing a thin-film transistor or like structure provides conductive “tails” below an overhang region formed by a top gate structure. The tails increase in thickness as they extend outward from a point under the overhang to the source and drain contacts. The tails provide a low resistance conduction path between the source and drain regions and the channel, with low parasitic capacitance. The thickness profile of the tails is controlled by the deposition of material over and on the lateral side surfaces of the gate structure. | 12-03-2009 |
20100060560 | LARGE AREA ELECTRONIC SHEET AND PIXEL CIRCUITS WITH DISORDERED SEMICONDUCTORS FOR SENSOR ACTUATOR INTERFACE - A pixel circuit including a first transistor; a second transistor, the first transistor and the second transistor serially coupled between a first power supply terminal and a second power supply terminal; and a first capacitor coupled between a gate of the first transistor and a gate of the second transistor, and an electronic sheet including the same. | 03-11-2010 |
20100067280 | CHARGE MAPPING MEMORY ARRAY FORMED OF MATERIALS WITH MUTABLE ELECTRICAL CHARACTERISTICS - A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. | 03-18-2010 |
20100067316 | CHARGE MAPPING MEMORY ARRAY FORMED OF MATERIALS WITH MUTABLE ELECTRICAL CHARACTERISTICS - A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. | 03-18-2010 |
20100068856 | CHARGE MAPPING MEMORY ARRAY FORMED OF MATERIALS WITH MUTABLE ELECTRICAL CHARACTERISTICS - A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. | 03-18-2010 |
20100073530 | Method and Apparatus for Using Thin-Film Transistors and MIS Capacitors as Light-Sensing Elements in Charge Mapping Arrays - A method and apparatus for using TFT transistors or MIS capacitors as light-sensing elements in charge mapping arrays. A bias stress may be applied to a plurality of pixels in a charge map array. As a result, charge carriers may be trapped in each of the plurality of pixels responsive to the bias stress, which may be observed as a value shift such as a threshold voltage V | 03-25-2010 |
20100096729 | GEOMETRY AND DESIGN FOR CONFORMAL ELECTRONICS - A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being located to allow the two-dimensional substrate to be shaped, the cuts having at least one stress relief feature, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure, the stress relief features arranged to alleviate stress in the three-dimensional structure. A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being arranged to as to increase a radius of curvature to meet a stress relief parameter when the substrate is shaped, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure. A three-dimensional electronic device having an electronic device formed on a flexible substrate, the flexible substrate formed into a three-dimensional structure, wedged-shaped portions removed from the substrate to allow the substrate to be formed into the three-dimensional structure, and a stress relief feature arranged adjacent to the wedge-shaped portions. | 04-22-2010 |
20100136757 | METHOD FOR ALIGNING ELONGATED NANOSTRUCTURES - A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor. | 06-03-2010 |
20100148188 | LASER-INDUCED FLAW FORMATION IN NITRIDE SEMICONDUCTORS - An embodiment is a method and apparatus to induce flaw formation in nitride semiconductors. Regions of a thin film structure are selectively decomposed within a thin film layer at an interface with a substrate to form flaws in a pre-determined pattern within the thin film structure. The flaws locally concentrate stress in the pre-determined pattern during a stress-inducing operation. The stress-inducing operation is performed. The stress-inducing operation causes the thin film layer to fracture at the pre-determined pattern. | 06-17-2010 |
20100158544 | FLEXIBLE DIAGNOSTIC SENSOR SHEET - A system of diagnosing a printer or photocopying system using a flexible diagnostic sheet is described. In the system, a thin diagnostic sheet including a plurality of sensors formed on the sheet is run through the paper path of the printing system. The printing system subjects the diagnostic sheet to the printing process, including the deposition of fuser oil and toner on the sheet. Sensors on the sheet record various parameters, including but not limited to the amount of fuser oil deposited and the charge on various toner particles. The information is transmitted to service personnel or the printer end user to enable timely repair of the printer. | 06-24-2010 |
20100158548 | FLEXIBLE NANOWIRE SENSORS AND FIELD-EFFECT DEVICES FOR TESTING TONER - A system, including an improved sensor, for determining toner particle uniformity is described. The sensor measures toner particle charge, typically be having the charge on the toner particle control a current flow through the channel of a thin film transistor. By measuring the charge on many toner particles, the system determines whether sufficient toner degradation has occurred that the toner should be replaced. The sensor is particularly suitable for being formed on a thin diagnostic sheet that is input through the paper path of a printing system. | 06-24-2010 |
20100181604 | STRUCTURE AND METHOD FOR FLEXIBLE SENSOR ARRAY - A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array. | 07-22-2010 |
20100231636 | Method For The Printing Of Homogeneous Electronic Material With A Multi-Ejector Print Head - Printing systems are disclosed that produce homogenous, smooth edged printed patterns (such as integrated circuit (IC) patterns) by separating pattern layouts into discrete design layers having only parallel layout features, and by printing each design layer using individual print solution droplets deposited onto the substrate. A first alignment operation is performed to achieve a specified orientation between the printhead and a first set of alignment marks on the substrate using first image data generated by the imaging sensor of the camera before performing a first print operation, and a second alignment operation to orient the printhead relative to a second set of alignment marks is performed before a second print operation. A first pattern layout portion includes first layout elements aligned parallel to a first reference axis, and the first print operation is performed by making multiple printing passes in a print direction aligned with the first reference axis. | 09-16-2010 |
20100231637 | Method For The Printing Of Homogeneous Electronic Material With A Multi-Ejector Print Head - Printing systems are disclosed that produce homogenous, smooth edged printed patterns (such as integrated circuit (IC) patterns) by separating pattern layouts into discrete design layers having only parallel layout features, and by printing each design layer using individual print solution droplets deposited onto the substrate. A printhead alignment operation includes printing a first spot from a first printhead ejector on a first substrate location, positioning a second ejector over the first substrate location and printing a second spot, measuring a distance between the first spot and the second spot, adjusting a rotational orientation between the print head and the substrate to reduce the distance between the first spot and the second spot, and then repeating the printing, measuring and adjusting processes until the first and second spots are separated by a predefined threshold value apart. The design layers are then printed. | 09-16-2010 |
20100231638 | Method For The Printing Of Homogeneous Electronic Material With A Multi-Ejector Print Head - Printing systems are disclosed that produce homogenous, smooth edged printed patterns (such as integrated circuit (IC) patterns) by separating pattern layouts into discrete design layers having only parallel layout features, and by printing each design layer using individual print solution droplets deposited onto the substrate. A printhead alignment operation includes positioning the printhead and printing a spot onto the substrate from each ejector, determining a vertical offset between an expected location of each spot along a vertical axis and the actual location of the spot along the vertical axis, calculating a linear fit line for the vertical offset of each spot plotted against an expected location of the spot along a horizontal axis, calculating the slope of the linear fit line, and rotating the printhead relative to the substrate according to an angle defined by the slope of the linear fit line. | 09-16-2010 |
20100252927 | Pattern-Print Thin-Film Transistors with Top Gate Geometry - A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode. | 10-07-2010 |
20110027947 | PRINTING METHOD FOR HIGH PERFORMANCE ELECTRONIC DEVICES - A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor. | 02-03-2011 |
20110073840 | RADIAL CONTACT FOR NANOWIRES - An embodiment is a method and apparatus of radial contact using nanowires. An inner contact has a center. An outer contact surrounds the inner contact around the center and is spaced from the inner contact by a channel length. A nanowire connects the center of the inner contact and the outer contact in a rotationally invariant geometry. | 03-31-2011 |
20110083728 | Disordered Nanowire Solar Cell - A disordered nanowire solar cell includes doped silicon nanowires disposed in a disordered nanowire mat, a thin (e.g., 50 nm) p-i-n coating layer formed on the surface of the silicon nanowires, and a conformal conductive layer disposed on the upper (e.g., n-doped) layer of the p-i-n coating layer. The disordered nanowire mat is grown from a seed layer using VLS processing at a high temperature (e.g., 450° C.), whereby the crystalline silicon nanowires assume a random interwoven pattern that enhances light scattering. Light scattered by the nanowires is absorbed by p-i-n layer, causing, e.g., electrons to pass along the nanowires to the first electrode layer, and holes to pass through the conformal conductive layer to an optional upper electrode layer. Fabrication of the disordered nanowire solar cell is large-area compatible. | 04-14-2011 |
20110185322 | METHOD OF IN-PROCESS INTRALAYER YIELD DETECTION, INTERLAYER SHUNT DETECTION AND CORRECTION - A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects. | 07-28-2011 |
20120164781 | Disordered Nanowire Solar Cell - A disordered nanowire solar cell includes doped silicon nanowires disposed in a disordered nanowire mat, a thin (e.g., 50 nm) p-i-n coating layer formed on the surface of the silicon nanowires, and a conformal conductive layer disposed on the upper (e.g., n-doped) layer of the p-i-n coating layer. The disordered nanowire mat is grown from a seed layer using VLS processing at a high temperature (e.g., 450° C.), whereby the crystalline silicon nanowires assume a random interwoven pattern that enhances light scattering. Light scattered by the nanowires is absorbed by p-i-n layer, causing, e.g., electrons to pass along the nanowires to the first electrode layer, and holes to pass through the conformal conductive layer to an optional upper electrode layer. Fabrication of the disordered nanowire solar cell is large-area compatible. | 06-28-2012 |
20120205656 | Thin-Film Electronic Devices Including Pre-Deformed Compliant Substrate - A thin-film layered electronic device, or array of devices, is formed over a layer structure comprising a flexible substrate, a buffer layer, and a metal layer. The layer structure is annealed to permanently deform the layer structure beyond its plastic deformation limit. The thin-film electronic device is formed thereover by a process according to which all steps are performed at a temperature below that at which further plastic deformation of the buffer layer occurs. In-process strain and runout are reduced, improving device yield on flexible substrates. The metal layer forms a first layer of the thin-film layered device, or array of devices. | 08-16-2012 |
20130298830 | GROWTH REACTOR SYSTEMS AND METHODS FOR LOW-TEMPERATURE SYNTHESIS OF NANOWIRES - A method for synthesis of silicon nanowires provides a growth reactor having a decomposition zone and a deposition zone. A precursor gas introduced into the decomposition zone is disassociated to form an activated species that reacts with catalyst materials located in the deposition zone to deposit nano-structured materials on a low melting point temperature substrate in the deposition zone. A decomposition temperature in the decomposition zone is greater than a melting point temperature of the low melting point temperature substrate. The silicon nanowire are grown directly on the low melting point temperature substrate in the deposition zone to prevent the higher temperatures in the decomposition zone from damaging the molecular structure and/or integrity of the lower melting point temperature substrate located in the deposition zone. | 11-14-2013 |
20140038334 | LASER-INDUCED FLAW FORMATION IN NITRIDE SEMICONDUCTORS - An embodiment is a method to induce flaw formation in nitride semiconductors. Regions of a thin film structure are selectively decomposed within a thin film layer at an interface with a substrate to form flaws in a pre-determined pattern within the thin film structure. The flaws locally concentrate stress in the pre-determined pattern during a stress-inducing operation. The stress-inducing operation is performed. The stress-inducing operation causes the thin film layer to fracture at the pre-determined pattern. | 02-06-2014 |
20140073117 | GROWTH REACTOR SYSTEMS AND METHODS FOR LOW-TEMPERATURE SYNTHESIS OF NANOWIRES - A method for synthesis of silicon nanowires provides a growth reactor having a decomposition zone and a deposition zone. A precursor gas introduced into the decomposition zone is disassociated to form an activated species that reacts with catalyst materials located in the deposition zone to deposit nano-structured materials on a low melting point temperature substrate in the deposition zone. A decomposition temperature in the decomposition zone is greater than a melting point temperature of the low melting point temperature substrate. The silicon nanowire are grown directly on the low melting point temperature substrate in the deposition zone to prevent the higher temperatures in the decomposition zone from damaging the molecular structure and/or integrity of the lower melting point temperature substrate located in the deposition zone. | 03-13-2014 |