Patent application number | Description | Published |
20090144503 | METHOD AND SYSTEM FOR INTEGRATING SRAM AND DRAM ARCHITECTURE IN SET ASSOCIATIVE CACHE - A method of integrating a hybrid architecture in a set associative cache having a first type of memory structure for one or more ways in each congruence class, and a second type of memory structure for the remaining ways of the congruence class, includes determining whether a memory access request results in a cache hit or a cache miss; in the event of a cache miss, determining whether LRU way of the first type memory structure is also the LRU way of the entire congruence class, and if not, then copying the contents of the LRU way of the first type memory structure into the LRU way of the entire congruence class, and filling the LRU way of the first type memory structure with a new cache line in the event of a cache miss; and updating LRU bits, depending upon the results of the memory access request. | 06-04-2009 |
20090244965 | MULTI-LAYER MAGNETIC RANDOM ACCESS MEMORY USING SPIN-TORQUE MAGNETIC TUNNEL JUNCTIONS AND METHOD FOR WRITE STATE OF THE MULTI-LAYER MAGNETIC RANDOM ACCESS MEMORY - A stacked magnetic tunnel junction (MTJ) structure of a multi-layer magnetic random access memory (MRAM) which includes a plurality of stacked MTJ devices serially connected to each other and an access transistor shared between the stacked MTJ devices. The stacked MTJ structure further includes a write word line through which a write current flows. The write current generates a hard axis magnetic field used to selectively write an MTJ device of the stacked MTJ devices. | 10-01-2009 |
20120036315 | Morphing Memory Architecture - A memory circuit comprises a memory array including a plurality of memory cells, multiple word lines, and at least one bit line. Each of the memory cells is coupled to a unique pair of a bit line and a word line for selectively accessing the memory cells. The memory circuit further includes at least one control circuit coupled to the word lines and operative to selectively change an operation of the memory array between a first data storage mode and at least a second data storage mode as a function of at least one control signal supplied to the control circuit. In the first data storage mode, each of the memory cells is allocated to a corresponding stored logic bit, and in the second data storage mode, at least two memory cells are allocated to a corresponding stored logic bit. | 02-09-2012 |
20130304737 | SYSTEM AND METHOD FOR THE CLASSIFICATION OF STORAGE - A classification system executing on one or more computer systems includes a processor and a memory coupled to the processor. The memory includes a discovery engine configured to navigate through non-volatile memory storage to discover an identity and location of one or more files in one or more computer storage systems by tracing the one or more files from file system mount points through file system objects and to disk objects. A classifier is configured to classify the one or more the files into a classification category. The one or more files are associated with the classification category and stored in at least one data structure. Methods are also provided. | 11-14-2013 |
20140167832 | CHANGING RESONANT CLOCK MODES - Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver. | 06-19-2014 |
20140173229 | Method and Apparatus for Automated Migration of Data Among Storage Centers - A method for controlling the storage of data among multiple regional storage centers coupled through a network in a global storage system is provided. The method includes steps of: defining at least one dataset comprising at least a subset of the data stored in the global storage system; defining at least one ruleset for determining where to store the dataset; obtaining information regarding a demand for the dataset through one or more data requesting entities operating in the global storage system; and determining, as a function of the ruleset, information regarding a location for storing the dataset among regional storage centers having available resources that reduces the total distance traversed by the dataset in serving at least a given one of the data requesting entities and/or reduces the latency of delivery of the dataset to the given one of the data requesting entities. | 06-19-2014 |
20140173232 | Method and Apparatus for Automated Migration of Data Among Storage Centers - A method for controlling the storage of data among multiple regional storage centers coupled through a network in a global storage system is provided. The method includes steps of: defining at least one dataset comprising at least a subset of the data stored in the global storage system; defining at least one ruleset for determining where to store the dataset; obtaining information regarding a demand for the dataset through one or more data requesting entities operating in the global storage system; and determining, as a function of the ruleset, information regarding a location for storing the dataset among regional storage centers having available resources that reduces the total distance traversed by the dataset in serving at least a given one of the data requesting entities and/or reduces the latency of delivery of the dataset to the given one of the data requesting entities. | 06-19-2014 |
20140218087 | Wide Bandwidth Resonant Global Clock Distribution - A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal. | 08-07-2014 |
20140223210 | Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Distribution - A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode. | 08-07-2014 |
20140240021 | SETTING SWITCH SIZE AND TRANSITION PATTERN IN A RESONANT CLOCK DISTRIBUTION SYSTEM - Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit. | 08-28-2014 |
20140245244 | SETTING SWITCH SIZE AND TRANSITION PATTERN IN A RESONANT CLOCK DISTRIBUTION SYSTEM - Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit. | 08-28-2014 |
20140245250 | SETTING SWITCH SIZE AND TRANSITION PATTERN IN A RESONANT CLOCK DISTRIBUTION SYSTEM - Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit. | 08-28-2014 |