Patent application number | Description | Published |
20090296292 | Electrostatic Discharge Protection Circuit Employing a Micro Electro-Mechanical Systems (MEMS) Structure - An ESD protection circuit for protecting a host circuit coupled to a signal pad from an ESD event occurring at the signal pad includes at least one MEMS switch which is electrically connected to the signal pad. The MEMS switch includes a first contact structure adapted for connection to the signal pad, and a second contact structure adapted for connection to a voltage supply source. The first and second contact structures are coupled together during the ESD event for shunting an ESD current from the signal pad to the voltage supply source. The first and second contact structures are electrically isolated from one another in the absence of the ESD event. At least one of the first and second contact structures includes a passivation layer for reducing contact adhesion between the first and second contact structures. | 12-03-2009 |
20090303093 | SYSTEMS AND METHODS FOR PIPELINED ANALOG TO DIGITAL CONVERSION - Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit. A bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer, and the bit enable set includes one or more output bits from preceding bit periods. | 12-10-2009 |
20090304066 | Systems and Methods for Speculative Signal Equalization - Various embodiments of the present invention provide systems and methods for signal equalization, and in some cases analog to digital conversion. For example, an analog to digital converter is disclosed that includes a comparator bank that receives a reference indicator and is operable to provide a decision output based at least in part on a comparison of an analog input with a reference threshold corresponding to the reference indicator. A range selection filter is included that has a first adjustment calculation circuit and a second adjustment calculation circuit. The first adjustment calculation circuit is operable to calculate a first adjustment feedback value based at least in part on a speculation that the decision output is a first logic level, and the second adjustment calculation circuit is operable to calculate a second adjustment feedback value based at least in part on a speculation that the decision output is a second logic level. A selector circuit selects the first adjustment feedback to generate the reference indicator when the decision output is the first logic level, and selects the second adjustment feedback to generate the reference indicator when the decision output is the second logic level. | 12-10-2009 |
20090319251 | Circuit Simulation Using Step Response Analysis in the Frequency Domain - A method for simulating a response of a circuit to an ESD input stimulus applied to the circuit includes the steps of: receiving a description of the circuit into a circuit simulation program, the circuit including at least one mutual inductance element indicative of magnetic coupling in the circuit; generating a linear approximation of nonlinear elements in the circuit at respective DC bias points of the nonlinear elements; obtaining a frequency domain transfer function of the circuit; obtaining a time domain impulse response of the circuit as a function of the frequency domain transfer function; integrating the time domain impulse response to yield a step response of the circuit, the step response being indicative of a response of the circuit to the ESD input stimulus; and analyzing the step response of the circuit to determine whether the circuit will operate within prescribed parameters corresponding to the circuit. | 12-24-2009 |
20100100859 | DESIGN METHODOLOGY FOR PREVENTING FUNCTIONAL FAILURE CAUSED BY CDM ESD - A design methodology which prevents functional failure caused by CDM ESD events. A transistor model is used to model the final states of cells, and a simulator is then used to identify invulnerable cells. Cells that are potential failure sites are then identified. The cells which have been identified as being potential victims are replaced by the previously-identified invulnerable cells that have the identical logic function. On the other hand, if a cell with identical function cannot be found, an invulnerable buffer cell (that will not effect logic function) can be inserted in front of the potential victim transistor as protection. By replacing all the potential victim cells with cells which have been determined to be invulnerable, the resulting design will be guaranteed to be CDM ESD tolerant. | 04-22-2010 |
20100194616 | Systems and Methods for Synchronous, Retimed Analog to Digital Conversion - Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase. A global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. In some instances of the aforementioned embodiments, an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase, and an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase. | 08-05-2010 |
20100195776 | Systems and Methods for Synchronous, Retimed Analog to Digital Conversion - Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch. | 08-05-2010 |
20120224613 | Low-loss Transmission Line TDM Communication Link and System - A time division multiplexing intra-chip communication system comprising at least one communication link. Such communication link comprises serialization and transmission circuitry, reception and deserialization circuitry, and at least one coaxial or wafer-level package transmission line interconnect therebetween. Such coaxial or wafer-level package transmission line interconnect may carry signals from such transmit circuitry to such receive circuitry. Such intra-chip communication links may achieve single-cycle operation or multi-cycle operation. Single single-cycle operation may be conducive to synchronous FSM design methodologies while multi-cycle operation may be conducive to data transfers to and from memory. | 09-06-2012 |
20130042216 | Row Based Analog Standard Cell Layout Design and Methodology - A system and method of designing the physical layout of an SoC incorporating row-based placement of analog standard cells whose heights are constrained to a predetermined row height or integer multiple thereof. A library of analog standard cells may be utilized by an ECAD tool to map, place, and route analog and mixed signal circuits in a manner similar to how such ECAD tool may utilize a library of digital standard cells to map, place, and route digital circuits. Mapping, placing, and routing of digital, analog, and mixed signal circuits may proceed within a unified ECAD SoC physical design flow. Finally, a general type analog standard cell is taught to further increase the speed and efficiency of analog and mixed-signal SoC layout. | 02-14-2013 |
Patent application number | Description | Published |
20090029882 | PROCESS TO MAKE AN ASHLESS LUBRICATING OIL WITH HIGH OXIDATION STABILITY - A process for making an ashless hydraulic fluid or paper machine oil comprising a) hydroisomerization dewaxing, b) fractionating, c) selecting a fraction having a very high VI, and a high level of molecules with cycloparaffinic functionality, and d) blending the fraction with an ashless antioxidant. A process for making ashless paper machine oil, comprising:
| 01-29-2009 |
20090029883 | METHOD FOR IMPROVING THE OXIDATION STABILITY OF ASHLESS OIL - A method for improving the oxidation stability of an ashless hydraulic fluid or an ashless paper machine oil, comprising: | 01-29-2009 |
20090075850 | ASHLESS HYDRAULIC FLUID OR PAPER MACHINE OIL - An ashless lubricating oil, comprising a base oil having greater than 90 wt % saturates, less than 10 wt % aromatics, a viscosity index greater than 130, low sulfur, and a sequential number of carbon atoms. The lubricating oil has a VI between 155 and 300, greater than 680 minutes in a rotary pressure vessel oxidation test, and a kinematic viscosity at 40° C. from 19.8 to 748 cSt. An ashless paper machine oil, comprising a base oil having a sequential number of carbon atoms, wherein the oil has a defined viscosity index and high oxidation stability. Also, an ashless lubricating oil, comprising a base oil having a viscosity index greater than 150, wherein the base oil is made from a blend of petroleum-based wax and Fischer-Tropsch derived wax. | 03-19-2009 |
20100191026 | ASHLESS HYDRAULIC FLUID OR PAPER MACHINE OIL - An ashless lubricating oil, comprising a base oil having a viscosity index greater than 150, wherein the base oil is made from a blend of petroleum-based wax and Fischer-Tropsch derived wax. | 07-29-2010 |
20120028863 | APPLICATION-SPECIFIC FINISHED LUBRICANT COMPOSITIONS COMPRISING A BIO-DERIVED ESTER COMPONENT AND METHODS OF MAKING SAME - The present invention is generally directed to methods of making application-specific finished lubricant compositions comprising bio-derived diester species. In some embodiments, bio-derived fatty acid moieties are reacted with Fischer-Tropsch/gas-to-liquids reaction products and/or by-products (e.g., gas-to-liquids-produced α-olefins) to yield bio-derived diester species that can then be selectively blended with base oil and one or more additive species to yield an application-specific finished lubricant product having a biomass-derived component. | 02-02-2012 |