Patent application number | Description | Published |
20080215914 | Self-reparable semiconductor and method thereof - A self-reparable semiconductor includes multiple functional units that perform the same function and that include sub-functional units. The semiconductor includes one or more full or partial spare functional units that are integrated into the semiconductor. If a defect in a sub-functional unit is detected, then that sub-functional unit is switched out and replaced with a sub-functional unit in the full or partial spare functional unit. The reconfiguration is realized with switching devices that are associated with the sub-functional units. Defective functional or sub-functional units can be detected after assembly, during power up, periodically during operation, and/or manually. | 09-04-2008 |
20090080459 | Long-reach ethernet for 1000BASE-T and 10GBASE-T - A physical-layer device (PHY) having corresponding methods comprises: a data rate module to select a data rate divisor N, where N is at least one of a positive integer, or a real number greater than, or equal to, 1; and a PHY core comprising a PHY transmit module to transmit first signals a data rate of M/N Gbps, and a PHY receive module to receive second signals at the data rate of MIN Gbps; wherein the first and second signals conform to at least one of 1000BASE-T, wherein M=1, and 10GBASE-T, wherein M=10. | 03-26-2009 |
20090147695 | SUB-SYMBOL RATE CABLE TESTER - Aspects of the present disclosure provide for a cable tester that tests a cable to determine the cable length. The cable tester can include a clock generator that generates a clock that has clock period that is a multiple of the data symbol period and a signal generator that injects the training signal, which can be synchronous with the clock, into the cable. The cable tester can also include a receiver that samples the returned signal from the cable and adaptively filters the returned signal based on the training signal and a controller that determines the cable length from the adaptive filter tap coefficients. | 06-11-2009 |
20110208985 | Low Power Mode for a Network Interface - A network interface including: a medium access control device configured to operate at a first power state during an inactive power mode, and operate at a second power state during an active power mode; a physical layer device including (i) an energy detect module configured to detect energy on a medium during the inactive power mode, and (ii) an energy save module configured to time a first pre-determined period subsequent to the energy detect module detecting energy on the medium. The medium access control device is further configured to, subsequent to the energy detect module detecting energy on the medium, transition to the second power state of the active power mode, and communication with the medium access control device via the medium is enabled subsequent to expiration of the first pre-determined period. | 08-25-2011 |
20120314716 | LONG-REACH ETHERNET FOR 1000BASE-T AND 10GBASE-T - A physical-layer device includes a cable measurement module, a data rate module and a physical-layer device core. The cable measurement module measures characteristics of a cable. The data rate module (i) selects a data rate divisor N based on the characteristics of the cable, and (ii) reduces a rate of a first clock based on the data rate divisor N, where N is greater than 1. The physical-layer device core includes: a transmit module that transmits first signals over the cable at a data rate of M/N Gbps based on the rate of the first clock, where M is an integer; and a receive module that receives second signals over the cable at the data rate of M/N Gbps based on the rate of the first clock. The first and second signals conform to 1000BASE-T when M=1. The first and signals conform to 10GBASE-T when M=10. | 12-13-2012 |
20130124918 | SELF-REPARABLE SEMICONDUCTOR AND METHOD THEREOF - A semiconductor device includes a plurality of processors and a spare processor configured to perform respective processing functions. A plurality of first switches is located at respective inputs of the plurality of processors. Each of the plurality of first switches is configured to selectively provide an input signal to a respective one of the plurality of processors and the spare processor. A first multiplexer is located at an input of the spare processor. The first multiplexer is configured to receive the input signals from each of the plurality of first switches and route, to the spare processor, a selected one of the input signals corresponding to a failed one of the plurality of processors. The spare processor is further configured to perform a processing function associated with the failed one of the plurality of processors in response to receiving the selected one of the input signals. | 05-16-2013 |
20140036933 | METHOD AND APPARATUS FOR ADJUSTING A RATE AT WHICH DATA IS TRANSFERRED, WITHIN A NETWORK DEVICE, FROM A MEDIA ACCESS CONTROLLER TO A MEMORY CONNECTED BETWEEN THE MEDIA ACCESS CONTROLLER AND A PHYSICAL-LAYER DEVICE - A first network device includes a host and a memory. A media access controller receives data from the host and stores the data in the memory at a first rate. A physical-layer device receives the data from the memory and transmits the data from the first network device to a second network device. The memory is connected between the media access controller and the physical-layer device. An amount of the data stored in the memory is based on the first rate and a second rate at which the physical-layer device transfers the data from the memory to the second network device. The first rate is greater than the second rate. A control circuit, based on an amount of the data stored in the memory, transmits a first frame to the media access controller. The media access controller, in response to the first frame, decreases the first rate. | 02-06-2014 |
20150244620 | METHOD AND APPARATUS FOR AGGREGATING AND ENCODING RECEIVED SYMBOLS INCLUDING GENERATION OF A POINTER FOR A CONTROL CODE - A data processing system including an interface and an encoder. The interface is configured to receive first symbols from one or more ports. The interface is configured to aggregate a predetermined number of the first symbols to provide second symbols. The encoder is configured to (i) generate a header, and (ii) encode the second symbols to generate third symbols, where the header indicates whether the third symbols include a set of control codes. Responsive to the third symbols including the set of control codes, the encoder is configured to generate a pointer for the set of control codes, where the pointer can assume more values than are in the set of control codes. | 08-27-2015 |