Patent application number | Description | Published |
20080286972 | ADDITION OF BALLAST HYDROCARBON GAS TO DOPED POLYSILICON ETCH MASKED BY RESIST - A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks. | 11-20-2008 |
20090159934 | FIELD EFFECT DEVICE WITH REDUCED THICKNESS GATE - A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer. | 06-25-2009 |
20090212332 | FIELD EFFECT TRANSISTOR WITH REDUCED OVERLAP CAPACITANCE - In a first structure, a metal gate portion may be laterally recessed from a substantially vertical surface of a gate conductor thereabove. A cavity is formed between the metal gate portion and a gate spacer. In a second structure, a disposable gate portion is removed after laterally recessing a metal gate portion therebeneath and forming a dielectric layer having a surface coplanar with a top surface of the disposable gate portion. (We have to include the inner spacer without a metal recess). An inner gate spacer is formed over a periphery of the metal gate portion provide a reduced overlap capacitance. In a third structure, a thin dielectric layer is employed to form a cavity next to the metal gate portion in conjunction with the inner gate spacer to provide reduced overlap capacitance. | 08-27-2009 |
20090250782 | SUBGROUNDRULE SPACE FOR IMPROVED METAL HIGH-K DEVICE - The present invention provides a semiconducting device including a substrate including at least one semiconducting region and isolation regions; a gate structure atop the substrate having a gate dielectric layer positioned on the semiconducting region and a metal layer atop the gate dielectric layer, the gate structure having a width equal to or greater than the width of the at least one semiconducting region; and a contact structure including a base having a first width equal to the width of the gate structure and an upper surface having a second width, wherein the first width is greater than the second width. In one embodiment, the contact structure includes a polysilicon conductor and dielectric spacers, wherein each spacer of the dielectric spacer abuts a sidewall of the polysilicon conductor. In another embodiment, the contact structure includes a polysilicon conductor having a tapered sidewall. | 10-08-2009 |
20110034000 | SELECTIVE DEPOSITION OF GERMANIUM SPACERS ON NITRIDE - A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface. | 02-10-2011 |
20110115032 | HIGH-K/METAL GATE TRANSISTOR WITH L-SHAPED GATE ENCAPSULATION LAYER - A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack. | 05-19-2011 |
20110221012 | HIGH-K DIELECTRIC GATE STRUCTURES RESISTANT TO OXIDE GROWTH AT THE DIELECTRIC/SILICON SUBSTRATE INTERFACE AND METHODS OF MANUFACTURE THEREOF - Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen. | 09-15-2011 |
20120286374 | HIGH-K DIELECTRIC GATE STRUCTURES RESISTANT TO OXIDE GROWTH AT THE DIELECTRIC/SILICON SUBSTRATE INTERFACE AND METHODS OF MANUFACTURE THEREOF - Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen. | 11-15-2012 |
20120299122 | HIGH-K/METAL GATE TRANSISTOR WITH L-SHAPED GATE ENCAPSULATION LAYER - A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack. | 11-29-2012 |