Patent application number | Description | Published |
20100110779 | MULTILEVEL PHASE CHANGE MEMORY OPERATION - Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed. | 05-06-2010 |
20120140555 | MULTILEVEL PHASE CHANGE MEMORY OPERATION - Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed. | 06-07-2012 |
20130215668 | MULTILEVEL PHASE CHANGE MEMORY OPERATION - Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed. | 08-22-2013 |
20130250688 | SELECTED WORD LINE DEPENDENT PROGRAMMING VOLTAGE - Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The duration of a programming pulse may depend on the word line that is selected for programming. This could be a physical characteristic of the word line or its location on a NAND string. As one example, a shorter pulse width may be used for the programming signal when programming edge word lines. | 09-26-2013 |
20140063940 | ON CHIP DYNAMIC READ LEVEL SCAN AND ERROR DETECTION FOR NONVOLATILE STORAGE - Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches. | 03-06-2014 |
20140247663 | NON-VOLATILE STORAGE WITH PROCESS THAT REDUCES READ DISTURB ON END WORDLINES - A system for reducing read disturb on edge word lines in non-volatile storage is disclosed. In one embodiment, the memory cells on edge word lines are programmed using a series of pulses that have an initial magnitude and step size between pulses that are lower than for memory cells on word lines that are not edge word lines. Additionally, when reading memory cells on word lines that are not edge word lines, the edge word lines receive a lower pass voltage than the default pass voltage applied to other unselected word lines. In another embodiment, the system applies a higher than normal bias on a neighboring word lines when reading memory cells on an edge word line. | 09-04-2014 |
20140254262 | INTERNAL DATA LOAD FOR NON-VOLATILE STORAGE - Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells. | 09-11-2014 |
20140347925 | INTERNAL DATA LOAD FOR NON-VOLATILE STORAGE - Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells. | 11-27-2014 |