Patent application number | Description | Published |
20120194210 | PROBE CARD WIRING STRUCTURE - The present disclosure provides a probe card for wafer level testing. The probe card includes a space transformer having first power/ground lines and first signal lines embedded therein, wherein the first power/ground and signal lines are configured to have a first wiring pitch on a first surface and a second wiring pitch on a second surface, the second wiring pitch being substantially less than the first wiring pitch; a printed circuit board bonded to the first surface of the space transformer, wherein the printed circuit board includes second power/ground lines and second signal lines embedded in the printed circuit board and coupled to the first power/ground and signal lines; and conductive lines configured to a surface of the printed circuit board remote to the first surface of the space transformer, wherein each of the conductive lines includes a first end coupled to one of the second signal lines and a second end coupled to a different location of the printed circuit board. | 08-02-2012 |
20120319711 | Probe Head Formation Methods Employing Guide Plate Raising Assembly Mechanism - An assembly includes a lower guide plate having a first plurality of through-holes therein, and an upper guide plate over the lower guide plate. The upper guide plate includes a second plurality of through-holes therein. The assembly further includes a plurality of probe pins. Each of the probe pins is inserted through one of the first plurality of through-holes and one of the second plurality of through-holes. The assembly further includes a plurality of probe pin stoppers, each attached to one of the probe pins, wherein the plurality of probe pin stoppers has lateral sizes greater than lateral sizes of the second plurality of through-holes. The plurality of probe pin stoppers is located over the upper guide plate. | 12-20-2012 |
20130002282 | Test Structures and Testing Methods for Semiconductor Devices - Test structures, methods of manufacturing thereof, and testing methods for semiconductors are disclosed. In one embodiment, a test structure for semiconductor devices includes a printed circuit board (PCB), a probe region, and a compliance mechanism disposed between the PCB and the probe region. A plurality of wires is coupled between the PCB and the probe region. End portions of the plurality of wires proximate the probe region are an integral part of the probe region. | 01-03-2013 |
20130069683 | TEST PROBE CARD - A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining | 03-21-2013 |
20140217575 | 3DIC Package Comprising Perforated Foil Sheet - A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS. | 08-07-2014 |
20140217610 | 3D Semiconductor Package Interposer with Die Cavity - Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted to at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects. | 08-07-2014 |
20140252585 | Packages for Semiconductor Devices, Packaged Semiconductor Devices, and Methods of Cooling Packaged Semiconductor Devices - Packages for semiconductor devices, packaged semiconductor devices, and methods of cooling packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a substrate including a semiconductor device mounting region, a cover coupled to a perimeter of the substrate, and members disposed between the substrate and the cover. The package includes partitions, with each partition being disposed between two adjacent members. The package includes a fluid inlet port coupled to the cover, and a fluid outlet port coupled to one of the partitions. | 09-11-2014 |
20140252634 | Packaging Devices and Methods for Semiconductor Devices - Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. The packaging device includes a stress isolation structure (SIS) disposed on the packaging substrate proximate a portion of a perimeter of the semiconductor device mounting region. | 09-11-2014 |
20140347085 | TEST PROBE CARD - A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining. | 11-27-2014 |
20150035134 | 3DIC PACKAGES WITH HEAT DISSIPATION STRUCTURES - A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion not overlapped by the first die. A first Thermal Interface Material (TIM) is over and contacting a top surface of the first die. A heat dissipating lid has a first bottom surface contacting the first TIM. A second TIM is over and contacting the second portion of the second die. A heat dissipating ring is over and contacting the second TIM. | 02-05-2015 |
20150035135 | 3DIC Packages with Heat Sinks Attached to Heat Dissipating Rings - A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion extending beyond edges of the first die. A first Thermal Interface Material (TIM) is overlying and contacting a top surface of the first die. A heat sink has a first bottom surface over and contacting the first TIM. A second TIM is overlying and contacting the second portion of the second die. A heat dissipating ring is overlying and contacting the second TIM. | 02-05-2015 |
20150048861 | HIGH FREQUENCY PROBING STRUCTURE - A probe card for wafer level test includes a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes a first surface having a first pitch and a second surface having a second pitch substantially less than the first pitch, a printed circuit board configured approximate the first surface of the space transformer, a first power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line to the printed circuit board, and a second power plane disposed on a surface of the printed circuit board and patterned to couple the power line and the ground line of the space transformer to the printed circuit board, wherein the second power plane is in electrical connection with the first power plane. | 02-19-2015 |
20150084181 | 3DIC Package Comprising Perforated Foil Sheet - A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS. | 03-26-2015 |