Patent application number | Description | Published |
20110037120 | Shielded gate trench MOSFET device and fabrication - A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode. | 02-17-2011 |
20110039383 | Shielded gate trench MOSFET device and fabrication - A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask. | 02-17-2011 |
20110095361 | MULTIPLE LAYER BARRIER METAL FOR DEVICE COMPONENT FORMED IN CONTACT TRENCH - A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer. | 04-28-2011 |
20110220990 | SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT - A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device. | 09-15-2011 |
20120129328 | MULTIPLE LAYER BARRIER METAL FOR DEVICE COMPONENT FORMED IN CONTACT TRENCH - A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer. | 05-24-2012 |
20120205737 | SHIELDED GATE TRENCH MOSFET DEVICE AND FABRICATION - A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode. | 08-16-2012 |
20130228860 | SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT - A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device. | 09-05-2013 |
20140091386 | MOSFET DEVICE AND FABRICATION - A semiconductor device includes a substrate, an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; and a body region in the substrate. The top surface of the polysilicon electrode is below the bottom of the body region. | 04-03-2014 |
20150194522 | SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT - A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device. | 07-09-2015 |
20150349091 | SEMICONDUCTOR POWER DEVICES MANUFACTURED WITH SELF-ALIGNED PROCESSES AND MORE RELIABLE ELECTRICAL CONTACTS - This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate. | 12-03-2015 |
Patent application number | Description | Published |
20100278035 | METHOD AND SYSTEM FOR MULTI-USER DETECTION USING TWO-STAGE PROCESSING - Systems and methods for multi-user detection in a multiple access system are provided. In one aspect, an apparatus is provided. The apparatus comprises a processing unit configured to process received chips into received symbols for a plurality of users and a computation unit configured to compute a multi-user matrix using a Hadamard matrix, wherein the multi-user matrix relates user symbols for the plurality of users to the received symbols. The apparatus further comprises a detection unit configured to detect the user symbols for the plurality of users using the received symbols and the computed multi-user matrix. | 11-04-2010 |
20100278216 | METHOD AND SYSTEM FOR INTER-CELL INTERFERENCE CANCELLATION - Systems and methods for inter-cell interference cancellation are provided. In one aspect of the disclosure, an apparatus is provided. The apparatus comprises a cell computation unit configured to compute receive chips for a first interfering cell and a subtraction unit configured to remove the computed receive chips for the first interfering cell from received chips at a receiver. The apparatus further comprises a processing unit configured to process the received chips with the computed receive chips for the first interfering cell removed into received symbols and a detection unit configured to detect user symbols for a target cell from the received symbols. | 11-04-2010 |
20100278219 | METHOD AND SYSTEM FOR MULTI-USER DETECTION IN THE PRESENCE OF MULTIPLE SPREADING FACTORS - Methods and systems for multi-user detection in the presence of multiple spreading factors are provided. In one aspect of the disclosure, an apparatus is provided. The apparatus comprises an interference computation unit configured to compute a combined interference based on detected user symbols for a first spreading factor and detected user symbols for a second spreading factor, wherein the combined interference accounts for multi-user interference from user symbols for the first and second spreading factors. The apparatus further comprises an interference cancellation unit configured to remove the computed combined interference from a plurality of received symbols corresponding to the first spreading factor and a redetection unit configured to redetect the user symbols for the first spreading factor from the plurality of received symbols with the computed combined interference removed. | 11-04-2010 |
20100278284 | METHOD AND SYSTEM FOR SYMBOL DETECTION USING SUB-CONSTELLATIONS - Systems and methods for symbol detection using sub-constellations are provided. In one aspect of the disclosure, an apparatus is provided. The apparatus comprises a processing unit configured to process received chips into received symbols for a plurality of users, a first detection unit configured to detect first components of user symbols for the plurality of users based on the received symbols and a computation unit configured to compute a portion of the received symbols due to the first components of the user symbols. The apparatus further comprises a second detection unit configured to detect second components of the user symbols based on the received symbols with the computed portion removed and a combining unit configured to detect the user symbols by combining the first components of the user symbols with the respective second components of the user symbols. | 11-04-2010 |
20100309956 | METHOD AND SYSTEM FOR INTERFERENCE CANCELLATION - Systems and methods for interference cancellation at a receiver in a wireless communication system are provided. In one aspect, a method for interference cancellation is provided. The method comprises providing total received chips received from a plurality of cells. The method also comprises successively estimating received chips for each of the plurality of cells in a plurality of iterations, wherein each of the plurality of iterations after a first iteration comprises canceling previously estimated received chips for one or more of the plurality of cells from the total received chips, and estimating received chips for one of the plurality of cells using the total received chips with the previously estimated received chips for the one or more of the plurality of cells cancelled out. | 12-09-2010 |
20110319045 | LINEAR INTERFERENCE CANCELLATION RECEIVER - Interference cancellation at a user equipment includes performing channel estimation for each component of an aggregate received signal using at least one received midamble of at least one time slot. The aggregate received signal is received from at least one Node B. A combined channel is computed for each channelization code based on the channel estimation. A linear transfer function is obtained for all user equipment within a cell. This linear transfer function includes a combined channel for each channelization code. An equalization matrix is derived from the linear transfer function and then applied to the aggregate received signal to obtain the component intended for the user equipment. | 12-29-2011 |
20120069753 | CHANNEL ESTIMATION BASED ON MIDAMBLE - Channel estimation at a user equipment includes estimating channel quality of at least one channel. A first algorithm or a second algorithm is selected based on the estimated channel quality. Channel estimation is performed based on the selected algorithm. The first algorithm may be a midamble multiplication-based algorithm. The second algorithm may be a midamble division algorithm. Channel estimation may also include estimating noise of a channel and adaptively setting a threshold based on the estimated noise to refine the channel estimation. The estimating channel quality, selecting of a first or second algorithm and channel estimation may be performed iteratively for contributing signals on a channel. An adaptive threshold may be modified across iterations. The channel estimation may also include determining a delay profile of a channel to refine the channel estimation. | 03-22-2012 |
20120093269 | APPARATUS AND METHOD FOR TWO-STAGE LINEAR/NONLINEAR INTERFERENCE CANCELLATION - An apparatus and method for a two-stage linear/nonlinear interference cancellation comprising processing a receive signal to produce a first descrambled signal; and processing the first descrambled signal to produce a detected signal. In one aspect, a first interference canceller module is used for processing the received signal and a second interference canceller module is used for processing the first descrambled signal. In one aspect, the first interference canceller is a linear interference canceller (IC) and the second interference canceller is a linear/nonlinear interference canceller (IC). | 04-19-2012 |
20140213210 | Method of Robust Receive (Rx) Processing for Radio Frequency Coexistence Management in Dual-SIM-Dual-Active Communication Devices - The various embodiments include a dual-SIM-dual-active (DSDA) device and methods for implementing robust receive (Rx) processing to resolve radio frequency coexistence interference between two subscriptions operating on the DSDA device. The DSDA device may detect when a subscription (the “aggressor”) de-senses the other subscription (the “victim”) as a result of the aggressor's transmissions, and in response, implement robust Rx processing to mitigate the effects of de-sense on the victim while causing minimal impact to the aggressor. | 07-31-2014 |
20140213235 | Method of Robust Transmit (Tx) Processing for Radio Frequency Coexistence Management in Dual-SIM-Dual-Active communication Devices - The various embodiments include a dual-SIM-dual-active (DSDA) device and methods for implementing robust transmit (Tx) processing to resolve radio frequency coexistence interference between two subscriptions operating on the DSDA device. The DSDA device may detect when one subscription (the “aggressor”) de-senses the other subscription (the “victim”) as a result of the aggressor's transmissions, and in response, implement robust Tx processing to mitigate the effects of de-sense on the victim. | 07-31-2014 |
20150282057 | Opportunistic Mobile Receive Diversity (OMRD) in a Dual-SIM Dual-Active (DSDA) Device - Methods and devices are disclosed for implementing opportunistic mobile receive diversity (“OMRD”) on a multi-SIM wireless device. The wireless device may receive a request from a protocol stack associated with the first SIM to utilize the second RF resource for receive diversity, and determine whether a protocol stack associated with the second SIM currently has a lower priority than the protocol stack associated with the first SIM. Upon determining that the protocol stack associated with the second SIM currently has a lower priority than the protocol stack associated with the first SIM, the wireless device may grant control of the second RF resource to the protocol stack associated with the first SIM. Granting control may provide, to the protocol stack associated with the first SIM, a capability to enable and disable receive diversity using the first and second RF resources. | 10-01-2015 |
20150349869 | ENHANCED OPPORTUNISTIC MOBILE RECEIVE DIVERSITY FOR DUAL-SIM DUAL-ACTIVE MOBILE DEVICE - A method for performing mobile receive diversity may include: enabling a first receive chain associated with a first radio access technology (RAT) to receive one or more signals from a second RAT; receiving second RAT signals on a second receive chain; enabling receive diversity on a modem associated with a second receive chain; generating, by a diversity receiver, a receive diversity signal based on the one or more second RAT signals received by the first receive chain during periods of time the first receive chain does not receive a signal from the first RAT; and outputting the generated receive diversity signal to a decoder for the second RAT. | 12-03-2015 |