Patent application number | Description | Published |
20090186428 | METHOD FOR CONSTRUCTING MODULE FOR OPTICAL CRITICAL DIMENSION (OCD) AND MEASUREING METHOD OF MODULE FOR OPTICAL CRITICAL DIMENSION USING THE MODULE - An optical critical dimension measuring method, applicable in measuring a pattern, that includes a plurality of polysilicon layers, of a device, is provided. The method includes obtaining a real curve corresponding to the to-be-measured device. Then, determining whether an ion implantation process has been performed on the polysilicon layers, a different module is selected. A correlation process is performed according to the selected module to generate a theoretical curve that correlates with the real curve to obtain a plurality of parameters corresponding to the theoretical curve. | 07-23-2009 |
20110189615 | SEMICONDUCTOR PROCESSING METHOD OF MANUFACTURING MOS TRANSISTOR - A method of manufacturing MOS transistor includes providing a substrate having a gate formed thereon; forming a hard mask layer on the substrate, performing an acid treatment to a surface of the hard mask layer, forming a photoresist layer on the hard mask layer after performing the acid treatment, performing a photolithography process to pattern the photoresist layer and the hard mask layer, performing an etching process to form recesses in the substrate, and performing a SEG method to form epitaxial layers respectively in the recesses. | 08-04-2011 |
20120193796 | POLYSILICON LAYER AND METHOD OF FORMING THE SAME - The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved. | 08-02-2012 |
20120270382 | METHOD OF FABRICATING AN EPITAXIAL LAYER - A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C. | 10-25-2012 |
20120292720 | METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A metal gate structure includes a high dielectric constant (high-K) gate dielectric layer, a metal gate having at least a U-shaped work function metal layer positioned on the high-K gate dielectric layer, and a silicon carbonitride (SiCN) seal layer positioned on sidewalls of the high-K gate dielectric layer and of the metal gate. | 11-22-2012 |
20120309171 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer. | 12-06-2012 |
20120329261 | MANUFACTURING METHOD FOR METAL GATE - A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function. | 12-27-2012 |
20130072030 | METHOD FOR PROCESSING HIGH-K DIELECTRIC LAYER - A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature. | 03-21-2013 |
20140091395 | TRANSISTOR - A method for fabricating a transistor device including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a lower tensile stress than the second tensile stress layer. | 04-03-2014 |
20140134824 | METHOD OF FABRICATING DIELECTRIC LAYER AND SHALLOW TRENCH ISOLATION - A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma. | 05-15-2014 |
20140213034 | METHOD FOR FORMING ISOLATION STRUCTURE - A method for forming an isolation structure includes the following steps. A hard mask layer is formed on a substrate and a trench is formed in the substrate and the hard mask layer. A protective layer is formed to cover the trench and the hard mask layer. A first isolation material is filled into the trench. An etching process is performed to etch back part of the first isolation material. | 07-31-2014 |
20150021776 | POLYSILICON LAYER - A polysilicon layer including an amorphous polysilicon layer and a crystallized polysilicon layer is provided. The crystallized polysilicon layer is disposed on the amorphous polysilicon layer. Besides, the amorphous polysilicon layer has a first grain size, the crystallized polysilicon layer has a second grain size, and the first grain size is smaller than the second grain size. The amorphous polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the crystallized polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved. | 01-22-2015 |
20150048486 | SPATIAL SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening. | 02-19-2015 |
20150087126 | METHOD OF FABRICATION TRANSISTOR WITH NON-UNIFORM STRESS LAYER WITH STRESS CONCENTRATED REGIONS - A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.) . Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer. | 03-26-2015 |