Patent application number | Description | Published |
20080307203 | Scaling Instruction Intervals to Identify Collection Points for Representative Instruction Traces - A method, system, and computer program product are provided for identifying instructions to obtain representative traces. A phase instruction budget is calculated for each phase in a set of phases. The phase instruction budget is based on a weight associated with each phase and a global instruction budget. A starting index and an ending index are identified for instructions within a set of intervals in each phase in order to meet the phase instruction budget for that phase, thereby forming a set of interval indices. A determination is made as to whether the instructions within the set of interval indices meet the global instruction budget. Responsive to the global instruction budget being met, the set of interval indices are output as collection points for the representative traces. | 12-11-2008 |
20100146512 | Mechanisms for Priority Control in Resource Allocation - Mechanisms for priority control in resource allocation is provided. With these mechanisms, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it desires to access and the unit's resource access group (RAG). This information is used to set a value of a storage device associated with the resource, priority, and RAG identified in the request. When the token manager generates and grants a token to the RAG, the token is in turn granted to a unit within the RAG based on a priority of the pending requests identified in the storage devices associated with the resource and RAG. Priority pointers are utilized to provide a round-robin fairness scheme between high and low priority requests within the RAG for the resource. | 06-10-2010 |
20120124299 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR EXTENDING A CACHE USING PROCESSOR REGISTERS - According to one aspect of the present disclosure, a method and technique for using processor registers for extending a cache structure is disclosed. The method includes identifying a register of a processor, identifying a cache to extend, allocating the register as an extension of the cache, and setting an address of the register as corresponding to an address space in the cache. | 05-17-2012 |
20120303591 | MANAGING ROLLBACK IN A TRANSACTIONAL MEMORY ENVIRONMENT - According to one aspect of the present disclosure, a method and technique for managing rollback in a transactional memory environment is disclosed. The method includes, responsive to detecting a begin transaction directive by a processor supporting transactional memory processing, detecting an access of a first memory location not needing rollback and indicating that the first memory location does not need to be rolled back while detecting an access to a second memory location and indicating that a rollback will be required. The method also includes, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omitting a rollback of the first memory location while performing rollback on the second memory location. | 11-29-2012 |
20120303938 | PERFORMANCE IN PREDICTING BRANCHES - A method, data processing system, and computer program product for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table. | 11-29-2012 |
20120304002 | MANAGING ROLLBACK IN A TRANSACTIONAL MEMORY ENVIRONMENT - A system and technique for managing rollback in a transactional memory environment is disclosed. The system includes a processor, a transactional memory, and a transactional memory manager (TMM) configured to perform a rollback on the transactional memory. The TMM is configured to, responsive to detecting a begin transaction directive by the processor, detect an access of a first memory location of the transactional memory not needing rollback and indicate that the first memory location does not need to be rolled back while detecting an access to a second memory location of the transactional memory and indicating that a rollback will be required. The TMM is also configured to, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omit a rollback of the first memory location while performing rollback on the second memory location. | 11-29-2012 |
20130111135 | VARIABLE CACHE LINE SIZE MANAGEMENT | 05-02-2013 |
20130111136 | VARIABLE CACHE LINE SIZE MANAGEMENT | 05-02-2013 |
20130145135 | PERFORMANCE OF PROCESSORS IS IMPROVED BY LIMITING NUMBER OF BRANCH PREDICTION LEVELS - A method utilizes information provided by performance monitoring hardware to dynamically adjust the number of levels of speculative branch predictions allowed (typically 3 or 4 per thread). for a processor core. The information includes cycles-per-instruction (CPI) for the processor core and number of memory accesses per unit time. If the CPI is below a CPI threshold; and the number of memory accesses (NMA) per unit time is above a prescribe threshold, the number of levels of speculative branch predictions is reduced per thread for the processor core. Likewise, the number of levels of speculative branch predictions could be increased, from a low level to maximum allowed, if the CPI threshold is exceeded or the number of memory accesses per unit time is below the prescribed threshold. | 06-06-2013 |
20140156979 | Performance in Predicting Branches - A method for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table. | 06-05-2014 |
20140173595 | HYBRID VIRTUAL MACHINE CONFIGURATION MANAGEMENT - A system and technique for hybrid virtual machine configuration management includes a processor and executable logic to: assign to a first set of virtual resources associated with a virtual machine a first priority, the first set associated with entitled resources for the virtual machine; assign to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; map the first set to a first physical resource of a pool of shared physical resources, the pool of shared physical resources allocatable to the first and second sets, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocate the first physical resource to the first set of virtual resources. | 06-19-2014 |
20140173597 | HYBRID VIRTUAL MACHINE CONFIGURATION MANAGEMENT - According to one aspect of the present disclosure, a method and technique for hybrid virtual machine configuration management is disclosed. The method includes: assigning to a first set of virtual resources associated with entitled resources of a virtual machine a first priority; assigning to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; mapping the first set of virtual resources to a first physical resource of a pool of shared physical resources allocatable to the first and second sets of virtual resources, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocating the first physical resource to the first set of virtual resources. | 06-19-2014 |
20150058840 | Sharing Resources Allocated to an Entitled Virtual Machine - A mechanism is provided for sharing resources allocated to an entitled virtual machine (VM). A blocked domain is created around the entitled VM and one or more processors allocated to the entitled VM. A first dispatching algorithm is implemented that prevents the dispatching of processes from other operating systems within other VMs to the one or more processors allocated to the entitled VM. Responsive to utilization of the one or more processors allocated to the entitled VM falling below a predetermined threshold, a second dispatching algorithm is implemented that allows dispatching of processes from the other operating systems within the other VMs to the one or more processors allocated to the entitled VM. | 02-26-2015 |
20150058842 | Sharing Resources Allocated to an Entitled Virtual Machine - A mechanism is provided for sharing resources allocated to an entitled virtual machine (VM). A blocked domain is created around the entitled VM and one or more processors allocated to the entitled VM. A first dispatching algorithm is implemented that prevents the dispatching of processes from other operating systems within other VMs to the one or more processors allocated to the entitled VM. Responsive to utilization of the one or more processors allocated to the entitled VM falling below a predetermined threshold, a second dispatching algorithm is implemented that allows dispatching of processes from the other operating systems within the other VMs to the one or more processors allocated to the entitled VM. | 02-26-2015 |