Patent application number | Description | Published |
20130246981 | DISSECTION SPLITTING WITH OPTICAL PROXIMITY CORRECTION TO REDUCE CORNER ROUNDING - The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having an main feature, the main feature including two corners and an edge spanning between the two corners; performing a feature adjustment to the edge; performing a dissection to the edge such that the edge is divided to include two corner segments and one center segment between the two corner segments; performing a first optical proximity correction (OPC) to the main feature for a center target associated with the center segment; thereafter, performing a second OPC to the main feature for two corner targets associated with the corner segments; and thereafter, performing a third OPC to main feature for the center target, resulting in a modified design layout. | 09-19-2013 |
20140007024 | Pattern Recognition For Integrated Circuit Design | 01-02-2014 |
20150040083 | SYSTEM AND METHOD FOR DECOMPOSITION OF A SINGLE PHOTORESIST MASK PATTERN INTO 3 PHOTORESIST MASK PATTERNS - A system and method of decomposing a single photoresist mask pattern to three photoresist mask patterns. The system and method assign nodes to polygon features on the single photoresist mask pattern, designate nodes as being adjacent nodes for those nodes that are less than a predetermined distance apart, iteratively remove nodes having 2 or less adjacent nodes until no nodes having 2 or less adjacent nodes remain, identify one or more internal nodes, map photoresist mask pattern designations (colors) to the internal nodes, and replace and map a color to each of the nodes removed by the temporarily removing nodes, such that each node does not have an adjacent node of the same color. | 02-05-2015 |
20150143304 | Target Point Generation for Optical Proximity Correction - A method performed by a computer processing system includes receiving a design pattern for an integrated circuit, applying a function to the design pattern to generate a model contour, generating a plurality of Optical Proximity Correction (OPC) target points along the model contour, adjusting the design pattern to create an adjusted pattern, and performing a simulation on the adjusted pattern to create a simulated contour. | 05-21-2015 |
20150161321 | POLYGON-BASED OPTICAL PROXIMITY CORRECTION - Methods and systems for design of integrated circuits including performing OPC are discussed. In one embodiment, design data having a geometric feature is provided. A base feature is formed from the geometric feature, which has a substantially linear edge. A pseudo dissection point is determined on the base feature. Add or trim a polygon from the base feature to form a modified feature. An OPC process is performed on the modified feature to generate an output design. The output design is used to fabricate a semiconductor device on a semiconductor substrate. | 06-11-2015 |
Patent application number | Description | Published |
20090023264 | METHOD OF MAKING PLANAR-TYPE BOTTOM ELECTRODE FOR SEMICONDUCTOR DEVICE - A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers. | 01-22-2009 |
20090023268 | ISOLATION METHOD OF ACTIVE AREA FOR SEMICONDUCTOR DEVICE - An isolation method of active area for semiconductor forms an isolated active area in a substrate. The substrate is a p-type silicon substrate. A pad oxide layer is formed on the substrate. A patterned sacrificial layer and an upper mask layer are formed on the pad oxide layer, where the upper mask layer is formed over the isolation region of the substrate. A gap is formed between the patterned sacrificial layer and the upper mask layer. An implantation process is performed to dope ions into the substrate through the gap, which forms an n-type barrier to surround the active areas. Lastly, the patterned sacrificial layer is stripped, and an anodization process is utilized to convert p-type bulk silicon into porous silicon. Then, an oxidation process is performed to oxidize the porous silicon to form a silicon dioxide isolation region for the active areas. | 01-22-2009 |
20090039428 | FABRICATING METHOD FOR SILICON ON INSULATOR AND STRUCTURE THEREOF - A fabricating method for silicon on insulator is disclosed, and the fabricating method includes stripping the oxide and the nitride on the bottom surface of each of the trenches, forming a porous silicon on portions of the substrate by an anodizing process, spin coating a dielectric material to fill up the trenches and performing a thermal process to convert the porous silicon to an insulating layer. | 02-12-2009 |
20090061635 | METHOD FOR FORMING MICRO-PATTERNS - A method for forming micro-patterns is disclosed. The method forms a sacrificial layer and a mask layer. A plurality of first taper trenches is formed in the sacrificial layer. A photoresist layer is filled in the plurality of first taper trenches. The photoresist layer is used as a mask and a plurality of second taper trenches is formed in the sacrificial layer. Then, the photoresist layer is stripped to be capable of patterning a layer by the first taper trenches and the second taper trenches in the sacrificial layer. Therefore, a patterned sacrificial layer duplicating the line density by double etching is formed. | 03-05-2009 |
Patent application number | Description | Published |
20130213495 | LIQUID LEVEL SENSOR - A quartz glass liquid level sensor includes a support frame, a light masking plate, a quartz glass tube, and a sensor module. The light masking plate is movably mounted on the support frame. The quartz glass tube is movably mounted to the support frame. One end of the quartz glass tube is securely fixed to the light masking plate. The sensor module is mounted on the support frame, for sensing a position of the light masking plate relative to the support frame. | 08-22-2013 |
20130228455 | SUPPORT MECHANISM - A support mechanism used in an electro plasma polishing process includes a support beam, a first electrically conducting assembly, and a second electrically conducting assembly. The first electrically conducting assembly and the second electrically conducting assembly are mounted on the support beam. The first electrically conducting assembly is electrically insulated from the second electrically conducting assembly. | 09-05-2013 |
20130233724 | SYSTEM AND METHOD OF ELECTROLYTIC DEBURRING FOR METAL PIECES - A system for electrolytic deburring of metal workpieces includes a power supply case, an electrolyte chamber, an anode, a cathode and a nozzle. The power supply case includes an anode connector and a cathode connector. Electrolyte is received in the electrolyte chamber. The anode holds at least one of workpiece and is immersed in the electrolyte, and electrically connected to the anode connector. The cathode is positioned in the electrolyte chamber and electrically connected to the cathode connector , and at least a part of the cathode is immersed in the electrolyte. The nozzle is positioned in the electrolyte chamber and sprays the electrolyte under pressure to form a vortex and turbulence for deburring metal. The disclosure also supplies a method of electrolytic deburring of metal. | 09-12-2013 |
20130284592 | VIBRATION FEEDING DEVICE - A vibration feeding device includes a mounting seat, a vibration feeding mechanism, and a pressing mechanism. The vibration feeding mechanism includes a driving member, a rotating shaft, a rotation wheel, and at least one adjusting member. The rotating shaft is rotatably connected to the driving member. The rotation wheel is non-rotatably sleeved on the rotating shaft. The at least one adjusting member is fixed between the rotating shaft and the rotation wheel to adjust an eccentricity of the rotation wheel. The vibration feeding mechanism is mounted on the mounting seat. The pressing mechanism is connected to the rotation wheel of the vibration feeding mechanism and is driven by the vibration to adjustably move close to and then away from a workpiece. | 10-31-2013 |
20140060592 | CLEANING DEVICE - A cleaning device includes a first linearly driving assembly, a second linearly driving assembly, a rotation driving assembly, and a sprayer connected one by one in that order. The first linearly driving assembly drives the second linearly driving assembly, the rotation driving assembly, and the sprayer to move along a first direction. The second linearly driving assembly drives the rotation driving assembly and the sprayer to move along a second direction. The rotation driving assembly rotates the sprayer along an axis perpendicular to the first direction and the second direction. | 03-06-2014 |