Patent application number | Description | Published |
20090026460 | VERTICAL NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method of a vertical non-volatile memory is provided. A first semiconductor layer, a first barrier, a second semiconductor layer, a second barrier and a third semiconductor layer are formed on a substrate sequentially. The first and the third semiconductor layers have a first conductive state, while the second semiconductor layer has a second conductive state. Several strips of active stacked structures are formed by removing portions of the first, second and third semiconductor layers, and portions of the first and second barrier on the substrate. After forming a storage structure on the substrate, the storage structure is covered with a conductive layer filling spaces among the active stacked structures. A portion of the conductive layer is removed to form word lines across the active stacked structures. | 01-29-2009 |
20090116284 | MEMORY APPARATUS AND METHOD THEREOF FOR OPERATING MEMORY - A memory apparatus, a controller, and a method thereof for programming non-volatile memory cells are provided. The memory apparatus includes a plurality of memory cells, wherein each memory cell shares a source/drain region with a neighboring memory cell. The method utilizes a compensation electron flow applied into a source/drain region between two memory cells to provide enough electron flow to program one of the two memory cells, even under the circumstances that the other memory cell has a greater threshold voltage, such that the dispersion of the programming speed of the memory cells is reduced. | 05-07-2009 |
20090116294 | METHOD OF PROGRAMMING CELL IN MEMORY AND MEMORY APPARATUS UTILIZING THE METHOD - A method of programming a first cell in a memory, wherein the first cell has a first S/D region and shares a second S/D region with a second cell that has a third S/D region opposite to the second S/D region. The channels of the first and the second cells are turned on, a first voltage is applied to the first S/D region, a second voltage is applied to the second S/D region and a third voltage is applied to the third S/D region. The second voltage is between the first voltage and the third voltage, and the first to third voltages make carriers flow from the third S/D region to the first S/ID region and cause hot carriers in the channel of the first cell to be injected into the charge storage layer of the first cell. | 05-07-2009 |
20100176437 | MEMORY ARRAY AND METHOD FOR MANUFACTURING AND OPERATING THE SAME - The invention provides a memory array. The memory array comprises a substrate, a plurality of word lines, a charge trapping structure, a plurality of trench channels and a plurality of bit lines. The word lines are located over the substrate and the word lines are parallel to each other. The charge trapping structure covers a surface of each of the word lines. The trench channels are located over the substrate and the word lines and the trench channels are alternatively arranged and each trench channel is separated from the adjacent word lines by the charge trapping structure. The bit lines are located over the word lines and each bit line is across over each of the word lines and each trench channel is electrically coupled to the bit lines. | 07-15-2010 |
20100227441 | METHOD OF MANUFACTURING MEMORY DEVICES - Disclosed is a memory device and method of operation thereof. The memory device may include a source region and a drain region of a first dopant type, the source and drain regions contain a first semiconductor material; a body region of a second dopant type, the body region being sandwiched between the source and drain regions, the body comprising a second semiconductor material; a gate dielectric layer over at least the body region; and a gate comprising a conductive material over the gate dielectric layer. Specifically, one of the first semiconductor material and the second semiconductor material is lattice matched with the other of the first semiconductor material and the second semiconductor material and has an energy gap smaller than the energy gap of the other of the first semiconductor material and the second semiconductor material. | 09-09-2010 |
20110079840 | MEMORY CELL AND MANUFACTURING METHOD THEREOF AND MEMORY STRUCTURE - A memory cell is provided. The memory cell includes a substrate, an isolation layer, a gate, a charge storage structure, a first source/drain region, a second source/drain region and a channel layer. The isolation layer is disposed over the substrate. The gate is disposed over the isolation layer. The charge storage structure is disposed over the isolation layer and the gate. The first source/drain region is disposed over the charge storage structure at two sides of the gate. The second source/drain region is disposed over the charge storage structure at top of the gate. The channel layer is disposed over the charge storage structure at sidewall of the gate and is electrically connected with the first source/drain region and the second source/drain region. | 04-07-2011 |
20120018790 | NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF - A non-volatile memory including a substrate, a stacked gate structure, two doped regions and a plurality of spacers is provided. The stacked gate structure is disposed on the substrate, wherein the stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer and a conductive layer in sequence from bottom to top relative to the substrate. The doped regions are disposed in the substrate at two sides of the stacked gate structure, respectively, and bottom portions of the doped regions contact with the substrate under the doped regions. The spacers are respectively disposed between each side of each of the doped regions and the substrate, and top portions of the spacers are lower than top portions of the doped regions. | 01-26-2012 |
20120287724 | METHOD OF PROGRAMMING MEMORY AND MEMORY APPARATUS UTILIZING THE METHOD - A method of programming a memory is provided. The memory has a first cell, having a first S/D region and a second S/D region shared with a second cell. The second cell has a third S/D region opposite to the second S/D region. When programming the first cell, a first voltage is applied to a control gate of the first cell, a second voltage is applied to a control gate of the second cell to slightly turn on a channel of the second cell, a third and a fourth voltage are respectively applied to the first and the third S/D regions, and the second S/D region is floating. A carrier flows from the third S/D region to the first S/D region, and is injected into a charge storage layer of the first cell by source-side injection. | 11-15-2012 |
20120326222 | MEMORY STRUCTURE AND FABRICATING METHOD THEREOF - A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer. | 12-27-2012 |
20120327721 | METHOD FOR ERASING MEMORY ARRAY - A method for erasing a memory array is provided. The memory array comprises a plurality of memory cell strings, and each of the memory cell strings comprises a plurality of memory cells connected to a plurality of word lines. The method for erasing the memory array includes the following steps. A first voltage is applied to a substrate of the memory array. A second voltage is applied to a word line of a selected memory cell, and a plurality of passing voltages are applied to other word lines. And, a third voltage and a fourth voltage are respectively applied to a first source/drain region and a second source/drain region of the selected memory cell, so that a band to band (BTB) hot hole injecting method is induced to erase the specific memory cell, wherein the third voltage is not equal to the fourth voltage. | 12-27-2012 |
20130092997 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A non-volatile memory and a manufacturing method thereof are provided. A first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the charge storage spacers. A conductive layer is formed on the second oxide layer. | 04-18-2013 |
20130099303 | MEMORY AND MANUFACTURING METHOD THEREOF - A memory and a manufacturing method thereof are provided. A plurality of stacked structures extending along a first direction is formed on a substrate. Each of the stacked structures includes a plurality of first insulating layers and a plurality of second insulating layers. The first insulating layers are stacked on the substrate and the second insulating layers are respectively disposed between the adjacent first insulating layers. A plurality of trenches extending along the first direction is formed in each of the stacked structures. The trenches are respectively located at two opposite sides of each of the second insulating layers. A first conductive layer is filled in the trenches. A plurality of charge storage structures extending along a second direction is formed on the stacked structures and a second conductive layer is formed on each of the charge storage structures. | 04-25-2013 |
20130105882 | MEMORY STRUCTURE AND FABRICATING METHOD THEREOF | 05-02-2013 |
20130134497 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device is described, including a gate over a substrate, a gate dielectric between the gate and the substrate, and two charge storage layers. The width of the gate is greater than that of the gate dielectric, so that two gaps are present at both sides of the gate dielectric and between the gate and the substrate. Each charge storage layer includes a body portion in one of the gaps, a first extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate, and a second extension portion connected to the first extension portion and extending along the sidewall of the gate, wherein the edge of the first extension portion protrudes from the sidewall of the second extension portion. | 05-30-2013 |
20130134498 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device is described, including a tunnel dielectric layer over a substrate, a gate over the tunnel dielectric layer, at least one charge storage layer between the gate and the tunnel dielectric layer, two doped regions in the substrate beside the gate, and a word line that is disposed on and electrically connected to the gate and has a thickness greater than that of the gate. | 05-30-2013 |
20130176789 | MEMORY ARRAY AND METHOD FOR PROGRAMMING MEMORY ARRAY - A method for programming a memory array is provided. The memory array includes a memory cell string composed of a first transistor, a plurality of memory cells and a second transistor connected in series, and the method for programming the memory array includes following steps. In a setup phase, a switching memory cell in the memory cells is turned off, and a first voltage and a second voltage are applied to a first source/drain and a second source/drain of the switching memory cell. In a programming phase, a bit line connected to the memory cell string is floating, and a ramp signal is provided to a word line electrically connected to the switching memory cell. | 07-11-2013 |
20130240975 | ROM FOR CONSTRAINING 2nd-BIT EFFECT - A read only memory including a substrate, a source region and a drain region, a charge storage structure, a gate, and a local extreme doping region is provided. The source region and the drain region are disposed in the substrate, the charge storage structure is located on the substrate between the source region and the drain region, and the gate is configured on the charge storage structure. The local extreme doping region is located in the substrate between the source region and the drain region and includes a low doping concentration region and at least one high doping concentration region. The high doping concentration region is disposed between the low doping concentration region and one of the source region and the drain region, and a doping concentration of the high doping concentration region is three times or more than three times a doping concentration of the low doping concentration region. | 09-19-2013 |
20140187032 | METHOD FOR FABRICATING MEMORY DEVICE - A method for fabricating a memory device of this invention includes at least the following steps. A tunnel dielectric layer is formed over a substrate. A gate is fowled over the tunnel dielectric layer. At least one charge storage layer is formed between the gate and the tunnel dielectric layer. Two doped regions are formed in the substrate beside the gate. A word line is formed on and electrically connected to the gate, wherein the word line having a thickness greater than a thickness of the gate. | 07-03-2014 |
20140209992 | FABRICATING METHOD OF NON-VOLATILE MEMORY STRUCTURE - A fabricating method for fabricating a non-volatile memory structure including the following steps is provided. A first conductive type doped layer is formed in a substrate. A plurality of stacked structures is formed on the substrate, and each of the stacked structures includes a charge storage structure. A first dielectric layer is formed on the substrate between the adjacent stacked structures. A second conductive type doped region is formed in the substrate between the adjacent charge storage structures. The second conductive type doped region has an overlap region with each of the charge storage structures. In addition, the second conductive type doped region divides the first conductive type doped layer into a plurality of first conductive type doped regions that are separated from each other. A conductive layer is formed on the first dielectric layer. | 07-31-2014 |
20140239370 | MEMORY DEVICE AND METHOD OF FORMING THE SAME - Provided is a memory device including a first dielectric layer, a T-shaped gate, two charge storage layers and two second dielectric layers. The first dielectric layer is disposed on a substrate. The T-shaped gate is disposed on the first dielectric layer and has an upper gate and a lower gate, wherein two gaps are present respectively at both sides of the lower gate and between the upper gate and the substrate. The charge storage layers are respectively embedded into the gaps. A second dielectric layer is disposed between each charge storage layer and the upper gate, between each charge storage layer and the lower gate and between each charge storage layer and the substrate. | 08-28-2014 |
20140264543 | STRUCTURE AND MANUFACTURING METHOD OF A NON-VOLTAILE MEMORY - A semiconductor structure uses its control gate to be the wordline for receiving an operation voltage for the semiconductor structure. The semiconductor structure has a first and a second doped region and a buried channel between the first and the second doped region, wherein the buried channel has a first length along the first direction. The semiconductor structure further has a charge trapping layer stack on the buried channel and a conductive layer on the charge trapping layer stack, wherein the conductive layer extends along the first direction. The conductive layer is configured as both the control gate and the wordline of the semiconductor structure. | 09-18-2014 |
20140306282 | MULTI LEVEL PROGRAMMABLE MEMORY STRUCTURE - A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer. | 10-16-2014 |
20140308791 | MANUFACTURING METHOD OF NON-VOLATILE MEMORY - A non-volatile memory and a manufacturing method thereof are provided. In this method, a first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the pair of charge storage spacers. A conductive layer is formed on the second oxide layer, wherein the conductive layer is located completely on the top of the pair of charge storage spacers. | 10-16-2014 |
20140346586 | NON-VOLATILE MEMORY STRUCTURE - A non-volatile memory structure, including a substrate, a plurality of stacked structures, a plurality of first conductive type doped regions, at least one second conductive type doped region, a conductive layer, and a first dielectric layer, is provided. The stacked structures are disposed on the substrate, and each of the stacked structures includes a charge storage structure. The first conductive type doped regions are disposed in the substrate under the corresponding charge storage structures respectively. The second conductive type doped region is disposed in the substrate between the adjacent charge storage structures and has an overlap region with each of the charge storage structures. The conductive layer covers the second conductive type doped region. The first dielectric layer is disposed between the conductive layer and the second conductive type doped region. | 11-27-2014 |