Patent application number | Description | Published |
20090139749 | Method For The Preparation Of A Flexible Transducer Unit, The Flexible Transducer Unit So Prepared And An Array Containing Such Flexible Transducer Units - The present invention relates to a method for the preparation of a flexible transducer unit from a wafer containing a plurality of transducer structures comprising a substrate, a metal-oxide layer, at least one mesh structure in said metal-oxide layer and electric wires including at least one first contact pad in said metal-oxide layer. The method includes the steps of: etch the metal-oxide layer to release said mesh; form a sealing layer on the mesh; form a first flexible material layer on the metal-oxide layer; and remove the substantial thickness of the substrate, sufficient to make the transducer structure flexible. Alternatively the first flexible material layer may be formed before the mesh is released. The method may further include the step of forming a second flexible layer in the back side of the wafer. A novel structure of the flexible transducer unit prepared according to the invented method is also disclosed. An array containing a plurality of the flexible transducer units is also disclosed. | 06-04-2009 |
20160084871 | DUAL-FUNCTIONAL RESONANT MAGNETIC FIELD SENSOR - Disclosed is a dual-functional resonant based magnetic field sensor that functions as magnetic field sensor and accelerometer, respectively, comprising a sensor structure including a mass block and motion sensor electrodes, capacitance to voltage converter and amplifier to convert sensing signals of the sensor electrodes into voltage, as output signals of the magnetic field sensor, a driving circuit to provide the output signals to the mass block in the form of current, to drive the mass block to vibrate, and a selection circuit to select measurement of magnetic field or acceleration. The driving circuit may be a comparator. The selection circuit may be replaced by a filter to select frequency bands of the output signals of the converter, for simultaneously providing signals representing magnetic field and acceleration, respectively. | 03-24-2016 |
20160084873 | Three-Axis Accelerometer - A three-axis accelerometer to provide measurement of acceleration in three axes, comprising a substrate, a suspending mass block suspended in the substrate, a group of Y direction displacement sensors, a group of Z direction displacement sensors and a group of X direction displacement sensors; wherein the Y direction displacement sensors, the Z direction displacement sensors and the X direction displacement sensors are respectively arranged adjacent to the mass block; the mass block and the displacement sensors respectively comprise a plurality of metal layers and a dielectric layer between two metal layers. In the mass block, regions corresponding to the Y, Z and X direction displacement sensors respectively comprise at least two metal layers connected by a via. The Y, Z and X groups displacement sensors respectively comprise at least two metal layers connected by a via. | 03-24-2016 |
20160084921 | RESONANT MAGNETIC FIELD SENSOR - Disclosed is a resonant magnetic field sensor, comprising a detector structure including a mass block and displacement detection electrodes; capacitance to voltage converter and amplifier to convert detection signals of the detection electrodes into voltage signals, as output signals of the magnetic field sensor; and a vibration driving circuit to provide the output signals to the mass block in the form of a current, to drive the mass block to vibrate. The vibration driving circuit may be a comparator. | 03-24-2016 |
20160084922 | MAGNETIC FIELD SENSOR - A magnetic field sensor, comprising a suspending mass block, a group of Y direction displacement sensors, a group of Z direction displacement sensors and a power supply; wherein the mass block, the Y direction displacement sensors and the Z direction displacement sensors respectively comprise a plurality of metal layers and a dielectric layer between two metal layers. In the mass block, a region corresponding to the Y direction displacement sensors and a region corresponding to the Z direction displacement sensors respectively comprise at least two metal layers connected by a via. The Y direction displacement sensors include two electrodes, each comprising at least two metal layers connected by a via; the Z direction displacement sensor includes two electrodes, each comprising at least two metal layers connected by a via; and the power supply provides a current flowing through the mass block selectively in X or Y direction. | 03-24-2016 |
Patent application number | Description | Published |
20130059382 | BIOMEDICAL MATERIALS FOR TISSUE ENGINEERING - In an embodiment of the disclosure, a biomedical material is provided. The biomedical material includes a biocompatible material having a surface and a carrier distributed over the surface of the biocompatible material, wherein both of the biocompatible material and the carrier have no charges, one of them has charges or both of them have charges with different electricity. The biomedical material is utilized for dentistry, orthopedics, wound healing or medical beauty and applied in the repair and regeneration of various soft and hard tissues. | 03-07-2013 |
20130287873 | PHARMACEUTICAL COMPOSITION AND METHOD FOR PREPARING A MEDICATION FOR PROMOTING WOUND HEALING - The disclosure provides a pharmaceutical composition for promoting wound healing, including an effective amount of a | 10-31-2013 |
20140220085 | METHOD FOR TISSUE ENGINEERING - In an embodiment of the disclosure, a biomedical material is provided. The biomedical material includes a biocompatible material having a surface and a carrier distributed over the surface of the biocompatible material, wherein both of the biocompatible material and the carrier have no charges, one of them has charges or both of them have charges with different electricity. The biomedical material is utilized for dentistry, orthopedics, wound healing or medical beauty and applied in the repair and regeneration of various soft and hard tissues. | 08-07-2014 |
20150147722 | BIONIC FIXING APPARATUS - A bionic fixing apparatus is provided. The bionic fixing apparatus includes a flexible portion having at least one trench. The trench is disposed on the surface of the flexible portion and has a first end and a second end. An interval is disposed between the first end and the second end. The trench is disposed for spreading the stress applied on the bionic fixing apparatus and preventing stress concentration and stress shielding. | 05-28-2015 |
20150150557 | BIONIC FIXING APPARATUS AND APPARATUS FOR PULLING OUT THE SAME - A bionic fixing apparatus is provided. The bionic fixing apparatus includes a body having a through hole and at least one slit. The through hole penetrates the body from the top surface to the bottom surface to form a top opening and a bottom opening. An inner diameter of the top opening is larger than an inner diameter of the bottom opening. The slit is connected to the bottom opening and extends upwardly from the bottom surface of the body, such that the body has a flexible bottom portion. | 06-04-2015 |
20150150614 | BIONIC FIXING APPARATUS - A bionic apparatus is provided. The bionic apparatus includes a flexible portion having a plurality of pores, a rigid portion connected with the flexible portion, and a supporting element disposed in the flexible portion. The pore size of each pore is between 50 μm to 500 μm. The flexible portion, the rigid portion and the supporting element are one-piece formed by a additive manufacturing process. | 06-04-2015 |
Patent application number | Description | Published |
20100289092 | POWER MOSFET PACKAGE - A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals. | 11-18-2010 |
20110042819 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes a semiconductor substrate having an upper surface and an opposite lower surface, a through-hole penetrating the upper surface and the lower surface of the semiconductor substrate, a chip disposed overlying the upper surface of the semiconductor substrate, a conducting layer overlying a sidewall of the through-hole and electrically connecting the chip, a first insulating layer overlying the upper surface of the semiconductor substrate, a second insulating layer overlying the lower surface of the semiconductor substrate, and a bonding structure disposed overlying the lower surface of the semiconductor substrate, wherein a material of the second insulating layer is different from that of the first insulating layer. | 02-24-2011 |
20110127670 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package includes a substrate having an upper and a lower surface and including: at least a first contact pad; a non-optical sensor chip disposed overlying the upper surface, wherein the non-optical sensor chip includes at least a second contact pad and has a first length; a protective cap disposed overlying the non-optical sensor chip, wherein the protective cap has a second length, an extending direction of the second length is substantially parallel to that of the first length, and the second length is shorter than the first length; an IC chip disposed overlying the protective cap, wherein the IC chip includes at least a third contact pad and has a third length, and an extending direction of the third length is substantially parallel to that of the first length; and bonding wires forming electrical connections between the substrate, the non-optical sensor chip, and the IC chip. | 06-02-2011 |
20110233782 | ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed. | 09-29-2011 |
20120146108 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a drain region located in the semiconductor substrate; a source region located in the semiconductor substrate; a gate located on the semiconductor substrate or at least partially buried in the semiconductor substrate, wherein a gate dielectric layer is between the gate and the semiconductor substrate; a drain conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the drain region; a source conducting structure disposed on the second surface of the semiconductor substrate and electrically connected to the source region; and a gate conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the gate. | 06-14-2012 |
20120146153 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar. | 06-14-2012 |
20120194301 | CAPACITIVE COUPLER PACKAGING STRUCTURE - Embodiments of the present invention provide a capacitive coupler packaging structure including a substrate with at least one capacitor and a receiver formed thereon, wherein the at least one capacitor at least includes a first electrode layer, a second electrode layer and a capacitor dielectric layer therebetween, and the first electrode layer is electrically connected to the receiver via a solder ball. The capacitive coupler packaging structure also includes a transmitter electrically connecting to the capacitor. | 08-02-2012 |
20120305977 | INTERPOSER AND MANUFACTURING METHOD THEREOF - An embodiment of the present invention provides a manufacturing method of an interposer including: providing a semiconductor substrate having a first surface, a second surface and at least a through hole connecting the first surface to the second surface; electrocoating a polymer layer on the first surface, the second surface and an inner wall of the through hole; and forming a wiring layer on the electrocoating polymer layer, wherein the wiring layer extends from the first surface to the second surface via the inner wall of the through hole. Another embodiment of the present invention provides an interposer. | 12-06-2012 |
20130193520 | POWER MOSFET PACKAGE - A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals. | 08-01-2013 |
20130328147 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region disposed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure disposed in the dielectric layer and electrically connected to the device region, a carrier substrate disposed on the dielectric layer; and a conducting structure disposed in a bottom surface of the carrier substrate and electrically contacting with the conducting pad structure. | 12-12-2013 |
20140073089 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package includes a substrate having an upper and a lower surface and including: at least a first contact pad; a non-optical sensor chip disposed overlying the upper surface, wherein the non-optical sensor chip includes at least a second contact pad and has a first length; a protective cap disposed overlying the non-optical sensor chip, wherein the protective cap has a second length, an extending direction of the second length is substantially parallel to that of the first length, and the second length is shorter than the first length; an IC chip disposed overlying the protective cap, wherein the IC chip includes at least a third contact pad and has a third length, and an extending direction of the third length is substantially parallel to that of the first length; and bonding wires forming electrical connections between the substrate, the non-optical sensor chip, and the IC chip. | 03-13-2014 |
20140193950 | ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed. | 07-10-2014 |
20150137341 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package including a first substrate having a first surface and a second surface opposite thereto is provided. The first substrate has a micro-electric element and a plurality of conducting pads adjacent to the first surface. The first substrate has a plurality of openings respectively exposing a portion of each conducting pad. A second substrate is disposed on the first surface. An encapsulation layer is disposed on the first surface and covers the second substrate. A redistribution layer is disposed on the second surface and extends into the openings to electrically connect the conducting pads. | 05-21-2015 |
20150145094 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package including a first substrate is provided. A plurality of first conductive pads is disposed on a first side of the first substrate. A second substrate is attached onto a second side opposite to the first side of the first substrate. The second substrate includes a micro-electric element and has a plurality of second conductive pads corresponding to the plurality of first conductive pads, disposed on a first side of the second substrate and between the first substrate and the second substrate. A redistribution layer is disposed on a second side opposite to the first side of the second substrate. The redistribution layer penetrates the second substrate, second conductive pads and the first substrate and extends into the first conductive pads to electrically connect the first and second conductive pads. | 05-28-2015 |
20150255358 | CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a semiconductor chip, a first and a second depression, a first and second redistribution layer and a packaging layer. The semiconductor chip has an electronic component and a conductive pad that are electrically connected and disposed on an upper surface of the semiconductor chip. The first depression and first redistribution layer extend from the upper surface toward the lower surface of the semiconductor chip. The first redistribution layer and the conductive pad are electrically connected. The second depression and the second redistribution layer extends from the lower surface toward the upper surface and is in connection with the first depression through a connection portion. The second redistribution layer is electrically connected to the first redistribution layer through the connection portion. The packaging layer is disposed on the lower surface. | 09-10-2015 |
20150303178 | CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A chip package includes a semiconductor chip, a first chip, a first connection portion, a molding layer, a metal redistribution layer and a packaging layer. The semiconductor chip includes a first conductive pad and a second conductive pad disposed on an upper surface of the semiconductor chip. The first chip is disposed on the upper surface, and the first chip has at least a first chip conductive pad. The first connection portion directly electrically connects the first chip conductive pad and the first conductive pad. The molding layer covers the upper surface, the first chip and the first connection portion, and the molding layer is formed with an opening exposing a second conductive pad. The metal redistribution layer is disposed in the opening, electrically connected to the second conductive pad and extending to the molding layer. The packaging layer covers the metal redistribution layer and the molding layer. | 10-22-2015 |
20150325551 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided. | 11-12-2015 |
20150325557 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package including a first substrate is provided. The first substrate includes a sensing device. A second substrate is attached onto the first substrate and includes an integrated circuit device. A first conductive structure is electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate. An insulating layer covers the first substrate, the second substrate and the redistribution layer. The insulating layer has a hole therein and a second conductive structure is disposed under the bottom of the hole. A method for forming the chip package is also provided. | 11-12-2015 |
20160005787 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region disposed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure disposed in the dielectric layer and electrically connected to the device region, a carrier substrate disposed on the dielectric layer; and a conducting structure disposed in a bottom surface of the carrier substrate and electrically contacting with the conducting pad structure. | 01-07-2016 |