Patent application number | Description | Published |
20090289273 | LIGHT EMITTING DEVICE PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF - A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously. | 11-26-2009 |
20090289345 | ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the two adjacent chips are arranged asymmetrically along side direction of the chip. A plurality of contact holes is formed in each chip, apart from the side of the chip, to expose the conductive electrodes. | 11-26-2009 |
20100230803 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode. | 09-16-2010 |
20130126086 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode. | 05-23-2013 |
20130127022 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode. | 05-23-2013 |
20140247585 | SEMICONDUCTOR LIGHTING APPARATUS - A semiconductor lighting apparatus includes an illumination module and a power module. The illumination module includes a supporting member, a semiconductor light-emitting element, an electrode structure and a first connecting member. The semiconductor light-emitting element is mounted on the supporting member and electrically connected with the electrode structure. The first connecting member is mounted on a first side of the supporting member. The power module is configured to connect to the first side of the supporting member, and includes a second connecting member and a driving circuit member. The second connecting member is detachably connected with the first connecting member. The driving circuit member is electrically connected with the second connecting member and electrically connected with the electrode structure to provide a driving power to the semiconductor light-emitting element. | 09-04-2014 |
20140319670 | IMAGE SENSOR PACKAGE WITH TRENCH INSULATOR AND FABRICATION METHOD THEREOF - The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; | 10-30-2014 |
20150060911 | OPTOELECTRONIC SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - An optoelectronic semiconductor device comprises a substrate, at least one solid via plug, at least one optoelectronic semiconductor chip, a phosphor layer and a molding body. The at least one solid via plug penetrates through the substrate. The at least one optoelectronic semiconductor chip has a first electrode aligned to and electrically connected with the solid via plug. The phosphor layer covers at least one surface of the optoelectronic semiconductor chip. The molding body encapsulates the substrate, the optoelectronic semiconductor chip and the phosphor layer. The number of solid valid plugs, substrate surfaces, electrodes, bonding pad on each surface of the substrate for forming each optoelectronic semiconductor device can be, for example, two, respectively. | 03-05-2015 |
Patent application number | Description | Published |
20090283877 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL. | 11-19-2009 |
20110140248 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL. | 06-16-2011 |
20110140267 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME - The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads. | 06-16-2011 |
20110193210 | IMAGE SENSOR PACKAGE WITH TRENCH INSULATOR AND FABRICATION METHOD THEREOF - The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad. | 08-11-2011 |
Patent application number | Description | Published |
20120091496 | SUBMOUNT AND MANUFACTURING METHOD THEREOF - A submount and a manufacturing method thereof are provided. The submount, on which at least a semiconductor die is disposed, is mounted on a circuit board. The submount includes a substrate made of a conductive material or a semiconducting material, a plurality of conductive film patterns, and an insulating film pattern. A surface of the substrate includes a die-bonding area and a plurality of conductive areas. The conductive film patterns are individually distributed in the respective conductive areas. The insulating film pattern is disposed between the conductive film pattern and the insulating film pattern, but is not disposed in the die-bonding area. Furthermore, the semiconductor die is disposed in the die-bonding area and is electrically connected with the conductive film patterns. Because the insulating film pattern is not being disposed in the die-bonding area of the submount, the submount structure has improved heat transfer efficiency. | 04-19-2012 |
20120228745 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a semiconductor die, a thermally conductive film, a substrate, a plurality of electrically conductive film patterns, and at least one insulator. The thermally conductive film is disposed on the bottom of the semiconductor die. The substrate is substantially comprised of the electrically conductive material or semiconductor material. Furthermore, a first hole is disposed on and passed all the way through the substrate, and the semiconductor die is disposed in the first hole. The electrically conductive film patterns are disposed on the substrate, and not contacting with each other. In addition, the insulator is connected between the semiconductor die and the substrate. | 09-13-2012 |
20140045302 | Manufacturing Method of Submount - A submount and a manufacturing method thereof are provided. The submount, on which at least a semiconductor die is disposed, is mounted on a circuit board. The submount includes a substrate made of a conductive material or a semiconducting material, a plurality of conductive film patterns, and an insulating film pattern. A surface of the substrate includes a die-bonding area and a plurality of conductive areas. The conductive film patterns are individually distributed in the respective conductive areas. The insulating film pattern is disposed between the conductive film pattern and the insulating film pattern, but is not disposed in the die-bonding area. Furthermore, the semiconductor die is disposed in the die-bonding area and is electrically connected with the conductive film patterns. Because the insulating film pattern is not being disposed in the die-bonding area of the submount, the submount structure has improved heat transfer efficiency. | 02-13-2014 |