Patent application number | Description | Published |
20090150836 | Intelligent Pattern Signature Based on Lithography Effects - The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective. | 06-11-2009 |
20090169114 | INTERPOLATION OF IRREGULAR DATA IN A FINITE-DIMENSIONAL METRIC SPACE IN LITHOGRAPHIC SIMULATION - A method, system, and computer program product for preprocessing a pattern in a library of patterns and querying a preprocessed library of patterns are disclosed. Embodiments for querying a preprocessed library of patterns are disclosed for determining a distance between the representation for the first pattern and the representation for the second pattern, determining whether the distance between the representation for the first pattern and the representation for the second pattern is within the range for the first pattern, and transforming the second pattern with the transformation matrix to provide information about the second pattern. Embodiments for preprocessing a pattern in a library of patterns are disclosed for determining a transformation matrix for the first pattern, determining a range for the first pattern, wherein a distance between a representation for a first pattern and a representation for a second pattern is within the range and the second pattern can be transformed with the transformation matrix to provide information about the second pattern, and associating the range and the transformation matrix with the first pattern. | 07-02-2009 |
20090199137 | SYSTEM AND METHOD FOR MULTI-EXPOSURE PATTERN DECOMPOSITION - Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern. | 08-06-2009 |
20090288047 | METHOD AND APPARATUS FOR USING A DATABASE TO QUICKLY IDENTIFY AND CORRECT A MANUFACTURING PROBLEM AREA IN A LAYOUT - One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a first area in a first layout, wherein the first area is associated with a first feature. Next, the system determines a first sample using the first check-figure, wherein the first sample represents the first layout's geometry within a first ambit of the first check-figure, wherein the first sample's geometry is expected to affect the shape of the first feature. The system then performs a model-based simulation using the first sample to obtain a first simulation-result which indicates whether the first feature is expected to have manufacturing problems. Next, the system stores the first simulation-result in a database which is used to quickly determine whether a second feature is expected to have manufacturing problems. | 11-19-2009 |
20090307642 | METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT - A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers. | 12-10-2009 |
20110167397 | SYSTEM AND METHOD FOR MULTI-EXPOSURE PATTERN DECOMPOSITION - Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern. | 07-07-2011 |
20110239168 | INTELLIGENT PATTERN SIGNATURE BASED ON LITHOGRAPHY EFFECTS - The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective. | 09-29-2011 |
20120272200 | METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT - A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers. | 10-25-2012 |
20120272201 | METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT - A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers. | 10-25-2012 |
20130195368 | SCALABLE PATTERN MATCHING BETWEEN A PATTERN CLIP AND A PATTERN LIBRARY - A two-level matching technique is described. A system can generate a set of index patterns based on a set of library patterns in a pattern library. The pattern library can include patterns that are expected to have problems during manufacturing. Next, the system can use a fast matching process to check if a first-level pattern clip potentially matches one or more index patterns from the set of index patterns. If so, the system can use a detailed matching process to match a second-level pattern clip with library patterns that correspond to the one or more index patterns. Otherwise, the system can report that the first-level pattern clip does not match any library pattern in the pattern library. | 08-01-2013 |
20140089868 | AUTOMATED REPAIR METHOD AND SYSTEM FOR DOUBLE PATTERNING CONFLICTS - A method of performing double patterning (DPT) conflict repairs is described. In this method, even cycles adjacent to odd cycles in a layout can be identified (also called adjacent even/odd cycles herein). The identifying can include forming graph constructs of the layout. Route guidances for break-link operations and split-node operations can be prioritized for the adjacent even/odd cycles. A list including the route guidances for the break-link operations and the split-node operations can be generated. The list can be ordered based on the prioritizing. | 03-27-2014 |