Patent application number | Description | Published |
20110221512 | Charge Pump - A charge pump is disclosed for amplifying an input voltage received at an input end and outputting the amplified voltage at an output end as an output voltage. The charge pump includes a plurality of source/drain coupling transistors for serving as charging capacitors, and a plurality of cascode-connected transistors being symmetrically connected to between the input end and the output end. The charge pump further includes a plurality of diode-connected transistors to protect the source/drain coupling transistors against breakdown during the course of charge transfer and to speed up the charge transfer. | 09-15-2011 |
20120087196 | GATE OXIDE BREAKDOWN-WITHSTANDING POWER SWITCH STRUCTURE - The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected. | 04-12-2012 |
20120170616 | Apparatus and Method for Sensing Temperature - An apparatus and a method for sensing temperature are provided. The apparatus includes a first oscillation circuit, a pulse width generator, and a comparison circuit. The first oscillation circuit is for generating a first signal having a first frequency which is related to a to-be-sensed temperature. The pulse width generator is for generating a pulse width signal, the pulse width signal having a pulse width related to the to-be-sensed temperature. The comparison circuit is for generating an output signal indicative of the value of the to-be-sensed temperature according to the first signal and the pulse width signal. | 07-05-2012 |
20120230086 | STATIC RANDOM ACCESS MEMORY CELL AND METHOD OF OPERATING THE SAME - A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit. | 09-13-2012 |
20130027122 | ON-CHIP ACTIVE DECOUPLING CAPACITORS FOR REGULATING VOLTAGE OF AN INTEGRATED CIRCUIT - On-chip active decoupling capacitors for regulating the voltage of an integrated circuit include a reference voltage generator, a latch-based comparator and switched DECAPs. The latched-based comparator is for comparing a reference voltage generated by the reference voltage generator and a supply voltage of the integrated circuit and outputting a comparison result. The switched DECAPs includes at least two capacitors and a plurality of switches, and coupling the at least two capacitors into a parallel configuration to sink current or a series configuration to source current based on the comparison result output by the latch-based comparator. The aforementioned on-chip active decoupling capacitors not only have lower power consumption, but also larger detection range. | 01-31-2013 |
20130028324 | METHOD AND DEVICE FOR DECODING A SCALABLE VIDEO SIGNAL UTILIZING AN INTER-LAYER PREDICTION - A method and device for decoding a scalable video signal utilizing an inter-layer prediction are provided herein. An inter-layer pre-fetch scheme (IPS) is presented to improve the performance for scalable video coding (SVC) decoder. With proposed invention, the required information for inter-layer prediction in SVC technique will be pre-fetched ahead when reconstructing the enhancement layer so that the cache miss rate can be reduced significantly. Accordingly, the execution time and memory energy consumptions can be improved. | 01-31-2013 |
20130031327 | SYSTEM AND METHOD FOR ALLOCATING CACHE MEMORY - Different processor elements in multi-task/multi-core system on chip may have different memory requirements at runtime. The method for adaptively allocating cache memory re-allocates the cache resource by updating the bank assignment table. According to the associativity-based partitioning scheme, centralized memory is separated into several groups of SRAM banks which are numbered differently. These groups are assigned to different processor elements to be L2 caches. The bank assignment information is recoded in bank assignment table, and is updated by system profiling engine. By changing the information in bank assignment table, the cache resource re-allocation for processor elements is achieved. | 01-31-2013 |
20140078818 | STATIC RANDOM ACCESS MEMORY WITH RIPPLE BIT LINES/SEARCH LINES FOR IMROVING CURRENT LEAKAGE/VARIATION TOLERANCE AND DENSITY/PERFORMANCE - A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line. | 03-20-2014 |