Patent application number | Description | Published |
20090077560 | Strongly-Ordered Processor with Early Store Retirement - In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit. | 03-19-2009 |
20100064120 | Replay Reduction for Power Saving - In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset. | 03-11-2010 |
20110214127 | Strongly-Ordered Processor with Early Store Retirement - In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit. | 09-01-2011 |
20120047332 | Combining Write Buffer with Dynamically Adjustable Flush Metrics - In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness. | 02-23-2012 |
20120079249 | Training Decode Unit for Previously-Detected Instruction Type - In an embodiment, a decode unit includes multiple decoders configured to decode different types of instructions. One or more of the decoders may be complex decoders, and the decode unit may disable the complex decoders if an instruction of the corresponding type is not being decoded. In an embodiment, the decode unit may disable the complex decoders by data-gating the instruction into the decoder. The decode unit may also include a control unit that is configured to detect instructions of the type decoded by the complex decoders, and to enable the complex decoders and redirect the fetching in response to the detection. The decode unit may also record an indication of the instruction (e.g. the program counter address (PC) of the instruction) to more rapidly detect the instruction and prevent a redirect in subsequent fetches. | 03-29-2012 |
20120110305 | Register Renamer that Handles Multiple Register Sizes Aliased to the Same Storage Locations - A processor may include a physical register file and a register renamer. The register renamer may be organized into even and odd banks of entries, where each entry stores an identifier of a physical register. The register renamer may be indexed by a register number of an architected register, such that the renamer maps a particular architected register to a corresponding physical register. Individual entries of the renamer may correspond to architected register aliases of a given size. Renaming aliases that are larger than the given size may involve accessing multiple entries of the renamer, while renaming aliases that are smaller than the given size may involve accessing a single renamer entry. | 05-03-2012 |
20130103906 | Combining Write Buffer with Dynamically Adjustable Flush Metrics - In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness. | 04-25-2013 |
20140195789 | Usefulness Indication For Indirect Branch Prediction Training - A circuit for implementing a branch target buffer. The branch target buffer may include a memory that stores a plurality of entries. Each entry may include a tag value, a target value, and a prediction accuracy value. A received index value corresponding to an indirect branch instruction may be used to select one of entries of the plurality of entries, and a received tag value may then be compared to the tag value of the selected entries in the memory. An entry in the memory may be selected in response to a determination that the received tag does not match the tag value of compared entries. The selected entry may be allocated to the indirect instruction branch dependent upon the prediction accuracy values of the plurality of entries. | 07-10-2014 |
20140215182 | Persistent Relocatable Reset Vector for Processor - In an embodiment, an integrated circuit includes at least one processor. The processor may include a reset vector base address register configured to store a reset vector address for the processor. Responsive to a reset, the processor may be configured to capture a reset vector address on an input, updating the reset vector base address register. Upon release from reset, the processor may initiate instruction execution at the reset vector address. The integrated circuit may further include a logic circuit that is coupled to provide the reset vector address. The logic circuit may include a register that is programmable with the reset vector address. More particularly, in an embodiment, the register may be programmable via a write operation issued by the processor (e.g. a memory-mapped write operation). Accordingly, the reset vector address may be programmable in the integrated circuit, and may be changed from time to time. | 07-31-2014 |
20140244976 | IT INSTRUCTION PRE-DECODE - Various techniques for processing and pre-decoding branches within an IT instruction block. Instructions are fetched and cached in an instruction cache, and pre-decode bits are generated to indicate the presence of an IT instruction and the likely boundaries of the IT instruction block. If an unconditional branch is detected within the likely boundaries of an IT instruction block, the unconditional branch is treated as if it were a conditional branch. The unconditional branch is sent to the branch direction predictor and the predictor generates a branch direction prediction for the unconditional branch. | 08-28-2014 |
20140317425 | MULTI-CORE PROCESSOR INSTRUCTION THROTTLING - An apparatus for performing instruction throttling for a multi-processor system is disclosed. The apparatus may include a power estimation circuit, a table, a comparator, and a finite state machine. The power estimation circuit may be configured to receive information on high power instructions issued to a first processor and a second processor, and generate a power estimate dependent upon the received information. The table may be configured to store one or more pre-determined power threshold values, and the comparator may be configured to compare the power estimate with at least one of the pre-determined power threshold values. The finite state machine may be configured to adjust the throttle level of the first and second processors dependent upon the result of the comparison. | 10-23-2014 |
20140365798 | L2 FLUSH AND MEMORY FABRIC TEARDOWN - A system and a method which include one or more processors, a memory coupled to at least one of the processors, a communication link coupled to the memory, and a power management unit. The power management unit may be configured to detect an inactive state of at least one of the processors. The power management unit may be configured to disable the communication link at a time after the processor enters the inactive state, and disable the memory at another time after the processor enters the inactive state. | 12-11-2014 |
20140380071 | Dynamic Voltage and Frequency Management based on Active Processors - In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected. | 12-25-2014 |