Patent application number | Description | Published |
20090020740 | RESISTIVE MEMORY STRUCTURE WITH BUFFER LAYER - A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride. | 01-22-2009 |
20090154222 | OPERATION METHOD FOR MULTI-LEVEL SWITCHING OF METAL-OXIDE BASED RRAM - Memory devices and methods for operating such devices are described herein. A method as described herein for operating a memory device includes applying a sequence of bias arrangements across a selected metal-oxide memory element to change the resistance state from a first resistance state in a plurality of resistance states to a second resistance state in the plurality of resistance states. The sequence of bias arrangements comprise a first set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the first resistance state to a third resistance state, and a second set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the third resistance state to the second resistance state. | 06-18-2009 |
20100148142 | ALUMINUM COPPER OXIDE BASED MEMORY DEVICES AND METHODS FOR MANUFACTURE - Memory devices are described along with methods for manufacturing. A memory device as described herein includes a first electrode and a second electrode. The memory device further includes a diode and an anti-fuse metal-oxide memory element comprising aluminum oxide and copper oxide. The diode and the metal-oxide memory element are arranged in electrical series between the first electrode and the second electrode. | 06-17-2010 |
20100276658 | Resistive Memory Structure with Buffer Layer - A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride. | 11-04-2010 |
20110175050 | Metal Oxide Resistance Based Semiconductor Memory Device With High Work Function Electrode - Various aspect are directed to a memory device or memory cell with a metal-oxide memory element arranged in electrical series along a current path between at least a first electrode, a metal-oxide memory element adjacent to the first electrode, and a second electrode. The first electrode comprises an electrode material having a first work function. The metal-oxide memory element comprises a metal-oxide material having a second work function. The first work function is greater than the second work function. Thermionic emission characterizes the current through this memory. | 07-21-2011 |
20110189819 | Resistive Memory Structure with Buffer Layer - A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride. | 08-04-2011 |
20110317471 | Nonvolatile stacked nand memory - A memory cell is arranged to enhance the electrical field of the memory element. The memory cell has a metal-oxide memory element, a nonconductive element, and a conductive element. The metal-oxide memory element is in a current path between a first electrode at a first voltage and a second electrode at a second voltage. The nonconductive element is adjacent to the metal-oxide memory element. | 12-29-2011 |
20120188813 | VERIFICATION ALGORITHM FOR METAL-OXIDE RESISTIVE MEMORY - Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided. | 07-26-2012 |
20130153846 | THREE DIMENSIONAL MEMORY ARRAY ADJACENT TO TRENCH SIDEWALLS - A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks. | 06-20-2013 |