Patent application number | Description | Published |
20110241202 | Dummy Metal Design for Packaging Structures - An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad. | 10-06-2011 |
20120178252 | Dummy Metal Design for Packaging Structures - A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern. | 07-12-2012 |
20120305916 | Interposer Test Structures and Methods - An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads. | 12-06-2012 |
20130092231 | PHOTOVOLTAIC PACKAGE - A photovoltaic package includes a substrate, a photovoltaic cell, an electric device, a cover, and an encapsulating material. The photovoltaic cell is disposed on the substrate. The electric device is disposed on the substrate and is electrically connected to the photovoltaic cell. The cover covers the substrate, the photovoltaic cell, and the electric device. The cover has a first depression formed therein. The first depression receives at least a portion of the electric device. The encapsulating material is located between the substrate and the cover. The encapsulating material at least partially encapsulates the photovoltaic cell and the electric device. | 04-18-2013 |
20130092935 | Probe Pad Design for 3DIC Package Yield Analysis - An interposer includes a first surface on a first side of the interposer and a second surface on a second side of the interposer, wherein the first and the second sides are opposite sides. A first probe pad is disposed at the first surface. An electrical connector is disposed at the first surface, wherein the electrical connector is configured to be used for bonding. A through-via is disposed in the interposer. Front-side connections are disposed on the first side of the interposer, wherein the front-side connections electrically couple the through-via to the probe pad. | 04-18-2013 |
20130113070 | Interposers for Semiconductor Devices and Methods of Manufacture Thereof - Interposers for semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, an interposer includes a substrate, a contact pad disposed on the substrate, and a first through-via in the substrate coupled to the contact pad. A first fuse is coupled to the first through-via. A second through-via in the substrate is coupled to the contact pad, and a second fuse is coupled to the second through-via. | 05-09-2013 |
20130120018 | Test Structure and Method of Testing Electrical Characteristics of Through Vias - A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV. | 05-16-2013 |
20130284230 | SOLAR CELL MODULE, ELECTRONIC DEVICE HAVING THE SAME, AND MANUFACTURING METHOD FOR SOLAR CELL - A solar cell module is provided and includes a first solar cell and a second solar cell. The first solar cell includes a first metal substrate, a first photoelectric conversion layer, a first top electrode layer, a first P-N junction semiconductor, and a first bottom electrode layer. The second solar cell includes a second metal substrate, a second photoelectric conversion layer, a second top electrode layer, a second P-N junction semiconductor, and a second bottom electrode layer. The first photoelectric conversion layer and the first P-N junction semiconductor are respectively located on two opposite sides of the first metal substrate. The second photoelectric conversion layer and the second P-N junction semiconductor are respectively located on two opposite sides of the second metal substrate. The second bottom electrode layer is located on the second P-N junction semiconductor, and is electrically coupled to the first metal substrate. | 10-31-2013 |
20130285636 | POWER TRACKING DEVICE AND POWER TRACKING METHOD - A power tracking device and a power tracking method is disclosed herein. The power tracking device includes a power voltage setting circuit, a switch, a switching signal circuit, and a voltage memory circuit. The switching signal circuit is configured for sending a first control signal to the switch. When the switch receives the first control signal and electrically isolates the power source and the power voltage setting circuit, the voltage memory circuit stores an open circuit voltage of the power source and sends a setting voltage relative to the open circuit voltage, and when the switch receives the first control signal and electrically connects the power source and the power voltage setting circuit, the power voltage setting circuit sets an output voltage of the power source to correspond with the setting voltage. | 10-31-2013 |
20130293011 | SOLAR POWER SYSTEM, SOLAR CELL MODULE AND POWER PROVIDING METHOD THEREOF - A solar power system includes a solar cell module, a main system and at least one sub system. The solar cell module includes at least one first solar cell unit and one second solar cell unit coupled in series. The first solar cell unit is configured to have an available maximum output current greater than that of the second solar cell unit. The main system is electrically coupled to the solar cell module and simultaneously supplied with electrical power by the first solar cell unit and the second solar cell unit both. The at least one sub system is electrically coupled to the solar cell module and supplied with electrical power by the first solar cell unit only. A solar cell module and a power providing method thereof are also provided. | 11-07-2013 |
20140106536 | Cylindrical Embedded Capacitors - A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate. | 04-17-2014 |
20140266283 | Chip-on-Wafer Process Control Monitoring for Chip-on-Wafer-on-Substrate Packages - An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure. | 09-18-2014 |
20150048503 | Packages with Interposers and Methods for Forming the Same - A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias. | 02-19-2015 |