| Patent application number | Description | Published |
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| 20110317694 | AUTOMATIC FILTER OVERLAP PROCESSING AND RELATED SYSTEMS AND METHODS - Systems and methods are disclosed that allow for improved management and control of packet forwarding in network systems. Network devices and tool optimizers and a related systems and methods are disclosed for improved packet forwarding between input ports and output ports. The input ports and output ports are configured to be connected to source devices and destination devices, for example, network sources and destination tools in a network monitoring environment. The network devices and tool optimizers disclosed can use a packet processing system whereby forwarding behavior is governed by matching packets in parallel against multiple user-specified packet filtering criteria, and by performing forwarding actions associated with all such matching filter criteria. The multi-action packet forwarding can be implemented using hardware configured to directly provide multi-action packet forwarding and/or hardware configured to provide single-packet-forwarding that has been subsequently configured using filter engines to provide multi-action packet forwarding. | 12-29-2011 |
| 20120106354 | SUPERSET PACKET FORWARDING FOR OVERLAPPING FILTERS AND RELATED SYSTEMS AND METHODS - Systems and methods are disclosed that allow for improved management and control of packet forwarding in network systems. Network devices and tool optimizers and a related systems and methods are disclosed for improved packet forwarding between input ports and output ports. The input ports and output ports are configured to be connected to source devices and destination devices, for example, network sources and destination tools in a network monitoring environment. The network devices and tool optimizers disclosed can use superset packet forwarding, such that ingress filter engines are configured with ingress filter rules so as to forward a superset of packets to output ports associated with overlapping filters. Egress filter engines are configured with egress filter rules to then determine which of the superset packets are actually sent out the output ports. | 05-03-2012 |
| 20120176159 | Systems and methods for precise event timing measurements - Systems and methods are disclosed for precise event time measurement. High speed serializer and deserializer circuitry are combined with high speed logic elements, such as exclusive-OR (XOR) or exclusive-not-OR (XNOR) logic circuitry, to achieve a measurement precision based upon a bit period associated with the high speed circuitry rather than upon slower reference clock signals. In certain embodiments, the disclosed systems and methods generate digital signal patterns, serialize them, transmit them as a high speed bit stream, utilize an event occurrence signal and logic circuitry to produce a modified bit stream, deserialize the modified bit stream to produce a modified digital signal pattern, compare the modified signal pattern with a predicted signal pattern, and determine bit positions or bit periods at which events occur based upon this comparison. These bit positions can then be used to generate precise timestamps and related time information for detected events. | 07-12-2012 |
| 20120176172 | Systems and methods for playback of detected timing events - Systems and methods are disclosed for playback of detected timing events with detected phase variations. Disclosed signal generation embodiments can be used to generate digital signals having desired phase variation. Disclosed event detection circuitry can be used to generate event timing data representing one or more phase variations in detected events. The disclosed signal generation embodiments can utilize the event timing data to playback detect events along with the measured phase variations. Further, the signal generation circuitry and the event detection circuitry can be implemented in different devices or can be implemented in the same device. | 07-12-2012 |
| 20120176174 | Systems and methods for precise generation of phase variation in digital signals - Systems and methods are disclosed for precise generation of phase variation in digital signals. The disclosed signal generation embodiments generate a pattern of information bits that represents a digital signal with desired phase variations and transmit this digital pattern at high speed utilizing a serializer to generate a high speed bit stream. The high speed bit stream can be used to generate one or more digital signals, such as clock signals, having desired rates and desired phase variations. In certain embodiments, the desired phase variation can be introduced into the resulting digital signal by removing and/or inserting bits in a digital pattern thereby moving logic transitions (e.g., rising edge transitions, falling edge transitions) as desired within the resulting digital signal. In addition to clock signals, the resulting digital signals generated can be control signals, data signals and/or any other desired digital signal. | 07-12-2012 |
| 20120179422 | Systems and methods for precise timing measurements using high-speed deserializers - Systems and methods are disclosed for precise event time measurement using high-speed deserializer circuitry. The described embodiments utilize high speed deserializer circuitry to achieve a precision based upon a bit period associated with the operation of the high speed operation of the deserializer circuitry rather than upon slower speed clock periods associated with reference clock signals. In certain embodiments, the disclosed systems and methods receive an event occurrence signal and use deserializer circuitry to sample the event occurrence signal and to produce multi-bit parallel data representing the event occurrence signal. Precise timestamps can then be generated based upon the multi-bit parallel data. Advantageously, the precision of these time measurements is associated with the bit period of the high speed operation of the deserializer circuitry and are not limited to lower speeds at which other circuitry within the system may be operating, for example, based upon a slower reference clock signal. | 07-12-2012 |
| 20120207178 | SYSTEMS AND METHODS UTILIZING LARGE PACKET SIZES TO REDUCE UNPREDICTABLE NETWORK DELAY VARIATIONS FOR TIMING PACKETS - Systems and methods are disclosed for utilizing large packet sizes to reduce unpredictable network delay variations in delivering timing packets across networks for use with respect to network timing protocols. By increasing the size of the timing packets, the disclosed embodiments reduce or eliminate the blocking effect caused by size differences between timing packets and relatively large packets carried through a packet network. By reducing or eliminating this blocking effect, the disclosed embodiments provide significant advantages in reducing the complexity of implementing robust timing protocols for handling unpredictable delays in the communication of timing packets. The size of timing packets can be increased, for example, by adding fill data to timing data to form large timing packets. A variety of large packet sizes can be used for the timing packets, and timing packets can preferably be made to be equal to the maximum transmission unit (MTU) for the network. | 08-16-2012 |
