Patent application number | Description | Published |
20080266993 | Serial connection external interface from printed circuit board translation to parallel memory protocol - A translator of an apparatus in an example through a serial connection external interface of a printed circuit board (PCB) communicates between a serial memory protocol within the PCB and a parallel memory protocol outside the PCB. | 10-30-2008 |
20080270826 | REDUNDANT MEMORY TO MASK DRAM FAILURES - A method comprises detecting a defective area in a Dynamic Random Access Memory (DRAM). The method further comprises establishing a redundant memory buffer at a per-memory module level. The method still further comprises loading the redundant memory buffer with a copy of data from the defective area. The method additionally comprises substituting data from the redundant memory buffer for data stored in the defective area upon a memory access to the defective area. | 10-30-2008 |
20090027844 | TRANSLATOR FOR SUPPORTING DIFFERENT MEMORY PROTOCOLS - A computer system includes a printed circuit board (PCB) that includes a first external interface for memory connection thereto, the first external interface employs a first memory protocol. The computer system further includes an extension circuit board and a translator module. the extension circuit board includes a second external interface for memory connection thereto and a third external interface, wherein the second external interface employs a second memory protocol different from the first memory protocol. The translator module is connectable to the first external interface of the PCB and the third external interface of the extension circuit board to provide translation between the first and second memory protocols. | 01-29-2009 |
20090031078 | Rank sparing system and method - A system, and a corresponding method, are used to implement rank sparing. The system includes a memory controller and one or more DIMM channels coupled to the memory controller, where each DIMM channel includes one or more DIMMS, and where each of the one or more DIMMs includes at least one rank of DRAM devices. The memory controller is loaded with programming to test the DIMMs to designate at least one specific rank of DRAM devices as a spare rank. | 01-29-2009 |
20090035978 | Modular DIMM carrier and riser slot - A modular DIMM carrier and riser slot device includes a slot section having a slot configured to hold a plurality of memory device planars, a first latch disposed at a first end of the slot section and pivotably connected to the slot section and capable of securing a first end of the memory device planars; a second latch disposed at a second end of the slot section and pivotably connected to the slot section and capable of securing a second end of a first memory device planar, and a third latch pivotably connected to the slot section and disposed intermediate between the first and the second latches, the third latch capable of securing a second end of a second memory device planar. The slot section has an auxiliary slot section defined as an section between the second latch and the third latch. The auxiliary slot section includes a notch for receiving the third latch when the third latch is in a disengaged position, a retention notch that restrains movement of the third latch when the third latch is in an engaged position, and a power and signaling section that includes power and signaling connections usable by one or more of the memory device planars. | 02-05-2009 |
20100107010 | ON-LINE MEMORY TESTING - A method of testing on-line and spare memory is disclosed. Such memory may currently store in-use data at some addresses. The testing is initiated upon an occurrence of a pre-selected condition. An address range is determined that excludes at least the addresses currently storing functional data. The address range is subjected to a test pattern, and errors in the address range are reported. | 04-29-2010 |
20100109704 | DIFFERENTIAL ON-LINE TERMINATION - Memory devices and systems incorporate on-die termination for signal lines. A memory device comprises an integrated circuit die. The integrated circuit die comprises a pair of input signal pins that supply a pair of input signals, and an on-die termination circuit coupled between the pair of input signal pins that differentially terminates the pair of input signals. | 05-06-2010 |
20110258400 | PARALLEL MEMORY DEVICE RANK SELECTION - A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules). | 10-20-2011 |
20140082411 | MEMORY MODULE THAT INCLUDES A MEMORY MODULE COPY ENGINE FOR COPYING DATA FROM AN ACTIVE MEMORY DIE TO A SPARE MEMORY DIE - A memory module includes a memory module copy engine for copying data from an active memory die to a spare memory die. Access is mapped away from the active memory die to the spare memory die. | 03-20-2014 |
20140089726 | DETERMINING WHETHER A RIGHT TO USE MEMORY MODULES IN A RELIABILITY MODE HAS BEEN ACQUIRED - Examples disclosed herein relate to determining whether a right to use memory modules in a reliability mode has been acquired. Examples include determining whether the right to use a plurality of memory modules in a reliability mode has been acquired, if a performance mode is selected for operation of the plurality of memory modules. | 03-27-2014 |