Patent application number | Description | Published |
20100026366 | Low Leakage Voltage Level Shifting Circuit - A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level. | 02-04-2010 |
20110089916 | LDO REGULATORS FOR INTEGRATED APPLICATIONS - Embodiments of the invention are related to LDO regulators. In an embodiment, an amplifier drives the gate of a master source follower and of at least one slave source follower to form an LDO regulator. In an alternative embodiment, a charge pump drives the master source follower to form the regulator. Additional slave source followers may be used in conjunction with the charge pump and the master source follower to improve the regulator performance. Other embodiments are also disclosed. | 04-21-2011 |
20110102070 | VOLTAGE PUMPING CIRCUIT - In a first pair of stacked PMOS devices comprising a first PMOS device and a second PMOS device, the first pumping circuit is coupled between a gate of the first PMOS device and a P pre-driver signal. In a second pair of stacked NMOS devices comprising a first NMOS device and a second NMOS device, the second pumping circuit is coupled between a gate of the first NMOS device and an N pre-driver signal. The pumping circuits recognizing the transition from the pre-driver signals provide a voltage to the gate of the first PMOS device and of the first NMOS device so that the first PMOS and NMOS devices are turned on better. As a result, their voltage Vds peaks are suppressed to a safe level; the devices avoid hot-carrier degradations; and their lifetimes are prolonged. | 05-05-2011 |
20110194218 | ESD Clamp for High Voltage Operation - An electrostatic discharge (ESD) clamp includes a first power source configured to provide a first power supply voltage, a power supply node coupled to the first power source and receiving the power supply voltage; and a first NMOS transistor and a second NMOS transistor coupled in series and between the power supply node and a VSS node. The first NMOS transistor and the second NMOS transistor are low nominal VDD devices with maximum endurable voltages lower than the power supply voltage. The ESD claim further includes an ESD detection circuit including a capacitor coupled between the power supply node and a gate of the second NMOS transistor, and a resistor coupled between the gate of the second NMOS transistor and the VSS node. | 08-11-2011 |
20120212279 | Threshold Voltage Detection Apparatus - A threshold voltage detection apparatus comprises a voltage level up-shifter and a voltage level down-shifter. The threshold voltage detection apparatus is placed at a circuit fabricated in a low voltage semiconductor process. The threshold voltage detection apparatus receives an input signal having a wide range and generates output signals comprising the logic of the input signal, but having a voltage range suitable for the low voltage circuit. The threshold voltage detection apparatus ensures that the low voltage circuit operates in a range to which the low voltage semiconductor process is specified. | 08-23-2012 |
20120241972 | LAYOUT SCHEME FOR AN INPUT OUTPUT CELL - An integrated circuit layout for an Input Output (IO) cell includes at least three metal layers. An IO pad is disposed directly over a top metal layer of the at least three metal layers. At least top two metal layers of the at least three metal layers provide a power bus and a ground bus. | 09-27-2012 |
20130181768 | 3X INPUT VOLTAGE TOLERANT DEVICE AND CIRCUIT - A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltage at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages. | 07-18-2013 |
20140063665 | Multiple Device Voltage Electrostatic Discharge Clamp - A multiple device voltage electrostatic discharge (ESD) clamp includes a trigger circuit, first and second inverters, and an ESD discharge path. The trigger circuit includes a resistor having a first terminal electrically connected to a first voltage supply node, and a capacitor having a first terminal electrically connected to a second voltage supply node. The first inverter has an input terminal electrically connected to second terminals of the resistor and the capacitor. The second inverter has a power terminal electrically connected to an output terminal of the first inverter. The ESD discharge path has a first end electrically connected to the first voltage supply node, and a second end electrically connected to a third voltage supply node, and includes a first transistor controlled by the first inverter, and a second transistor controlled by the second inverter. | 03-06-2014 |
20140266387 | INPUT/OUTPUT INTERFACE - One or more systems and techniques for communicating a signal between a first chip and a second chip using one or more circuits are provided. If the signal corresponds to a first voltage, one or more voltages are provided to one or more locations and a capacitive load is charged using a pull-up driver that is connected to a power supply. If the signal corresponds to a second voltage, one or more voltages are provided to one or more locations and the capacitive load is discharged using a pull-down driver that is connected to ground. When the first chip is powered off, a fail-safe mode is provided by configuring a cross control circuit to generate a bias to control one or more transistors. | 09-18-2014 |
Patent application number | Description | Published |
20130319543 | Asymmetrical Chamber Configuration - A production tool includes a chamber, a heater in the chamber, and a pumping outlet on a side of the heater. A pumping liner is in the chamber and encircling the heater. The pumping liner and the heater have a first gap therebetween and a second gap therebetween. The second gap is different from the first gap, and the second gap is farther away from the first pumping outlet than the first gap. | 12-05-2013 |
20140026813 | Apparatus for Dielectric Deposition Process - An apparatus comprises a first gas inlet coupled between a first pipe and a reaction chamber, wherein the first pipe configured to carry process gases, a second gas inlet coupled between a second pipe and the reaction chamber, wherein the second pipe configured to carry a precursor material in a gaseous state and a heating device coupled to the second pipe and the second gas inlet, wherein the heating device keeps an ambient temperature of the second pipe and the second gas inlet above a boiling point of the precursor material. | 01-30-2014 |
20140377961 | THIN FILM DEPOSITION APPARATUS WITH MULTI CHAMBER DESIGN AND FILM DEPOSITION METHODS - A multi chamber thin film deposition apparatus and a method for depositing films, is provided. Each chamber includes a three dimensional gas delivery system including process gases being delivered downwardly toward the substrate and laterally toward the substrate. A pumping system includes an exhaust port in each chamber that is centrally positioned underneath the substrate being processed and therefore the gas flow around all portions of the edge of the substrate are equally spaced from the exhaust port thereby creating a uniform gas flow profile which results in film thickness uniformity of films deposited on both the front and back surfaces of the substrate. The deposited films demonstrate uniform thickness on the front and back of the substrate and extend inwardly to a uniform distance on the periphery of the backside of the substrate. | 12-25-2014 |
20150348779 | COATING APPARATUS AND METHOD OF FORMING COATING FILM - A method of forming a coating film over a substrate is provided. The method includes spinning the substrate. The method further includes providing a central coating liquid spray over a central portion of the substrate. The method also includes providing first coating liquid sprays over the substrate. The first coating liquid sprays surround the central coating liquid spray and are spaced apart from the central coating liquid spray by a same first distance. | 12-03-2015 |
Patent application number | Description | Published |
20120021183 | Forming Low Stress Joints Using Thermal Compress Bonding - A method of forming a bump structure includes providing a first work piece including a dielectric layer having a top surface; placing a second work piece facing the first work piece; placing a heating tool contacting the second work piece; and heating the second work piece using the heating tool to perform a reflow process. A first solder bump between the first and the second work pieces is melted to form a second solder bump. Before the second solder bump solidifies, pulling the second work piece away from the first work piece, until an angle formed between a tangent line of the second solder bump and the top surface of the dielectric layer is greater than about 50 degrees, wherein the tangent line is drawn at a point where the second solder bump joins the dielectric layer. | 01-26-2012 |
20130048027 | Package Assembly Cleaning Process Using Vaporized Solvent - A method includes generating a solvent-containing vapor that contains a solvent. The solvent-containing vapor is conducted to a package assembly to clean the package assembly. The solvent-containing vapor condenses to form a liquid on a surface of the package assembly, and flows off from the surface of the package assembly. | 02-28-2013 |
20130128486 | Forming Low Stress Joints Using Thermal Compress Bonding - A method of forming a bump structure includes providing a first work piece including a dielectric layer having a top surface; placing a second work piece facing the first work piece; placing a heating tool contacting the second work piece; and heating the second work piece using the heating tool to perform a reflow process. A first solder bump between the first and the second work pieces is melted to form a second solder bump. Before the second solder bump solidifies, pulling the second work piece away from the first work piece, until an angle formed between a tangent line of the second solder bump and the top surface of the dielectric layer is greater than about 50 degrees, wherein the tangent line is drawn at a point where the second solder bump joins the dielectric layer. | 05-23-2013 |
20130244403 | METHOD AND DEVICE FOR CUTTING SEMICONDUCTOR WAFERS - A method for cutting a semiconductor wafer into semiconductor chips that reduces defects at the semiconductor chip corners. The method includes a pre-cutting processing step of trimming the semiconductor chip corners so that mechanical stress is reduced at the corners. The method includes dicing channels on a semiconductor wafer thereby defining the geometrical shape of one of the semiconductor chips, modifying the corners of the one of the semiconductor chips, and cutting the semiconductor wafer to separate the one of the semiconductor chips from other semiconductor chips. | 09-19-2013 |
20130248119 | APPARATUS AND METHOD OF SEPARATING WAFER FROM CARRIER - A method of separating a wafer from a carrier includes placing a wafer assembly on a platform. The wafer assembly includes the wafer, the carrier, and a layer of wax between the wafer and the carrier. A wafer frame is mounted on the wafer of the wafer assembly. The layer of wax is softened. The wafer and the wafer frame mounted thereon are separated, by a first robot arm, from the carrier. | 09-26-2013 |
20130273717 | Apparatus and Method for the Singulation of a Semiconductor Wafer - The present disclosure is directed to an apparatus for the singulation of a semiconductor substrate or wafer. In some embodiments the singulation apparatus comprises a plurality of cutting devices. The cutting devices are configured to form multiple concurrent cutting lines in parallel on a surface of the semiconductor wafer. In some embodiments, the singulation apparatus comprises at least two dicing saws or laser modules. The disclosed singulation apparatus can dice the semiconductor wafer into individual chips by dicing in a direction across a complete circumferential edge of the wafer, thereby decreasing process time and increasing throughput. | 10-17-2013 |
20140048586 | Innovative Multi-Purpose Dipping Plate - The present disclosure is directed to an apparatus for the application of soldering flux to a semiconductor workpiece. In some embodiments the apparatus comprises a dipping plate having a reservoir which is adapted to containing different depths of flux material. In some embodiments, the reservoir comprises at least two landing regions having sidewalls which form first and second dipping zones. The disclosed apparatus can allow dipping of the semiconductor workpiece in different depths of soldering flux without the necessity for changing dipping plates. | 02-20-2014 |
20140360671 | APPARATUS FOR SEPARATING WAFER FROM CARRIER - An apparatus for separating a wafer from a carrier includes a platform having an upper surface, a tape feeding unit, a first robot arm, and a controller coupled to the platform. The controller is configured to mount a wafer frame, by using the tape feeding unit, on a wafer of a wafer assembly on the upper surface of the platform. The wafer assembly includes the wafer, a carrier, and a layer of wax between the wafer and the carrier. The controller is also configured to heat the upper surface of the platform to a predetermined temperature and separate, by the first robot arm, the wafer and the wafer frame mounted thereon from the carrier. | 12-11-2014 |
Patent application number | Description | Published |
20130126953 | Methods and Apparatus for MOS Capacitors in Replacement Gate Process - Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed. | 05-23-2013 |
20130126955 | Methods and Apparatus for Hybrid MOS Capacitors in Replacement Gate Process - Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed. | 05-23-2013 |
20130228878 | POLY RESISTOR DESIGN FOR REPLACEMENT GATE TECHNOLOGY - A semiconductor device and method for fabricating a semiconductor device are disclosed. The semiconductor device comprises a semiconductor substrate; an active region of the substrate, wherein the active region includes at least one transistor; and a passive region of the substrate, wherein the passive region includes at least one resistive structure disposed on an isolation region, the at least one resistive structure in a lower plane than the at least one transistor | 09-05-2013 |
20130230952 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved protection for the bottom portion of the gate structure. In some embodiments, the method achieves improved protection for gate structure bottom by forming a recess on either side of the gate structure and placing spacers on the side walls of the gate structure, so that the spacers protect the portion of the gate structure below the gate dielectric layer. | 09-05-2013 |
20140239417 | Semiconductor Device Having Electrode and Manufacturing Method Thereof - The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench. | 08-28-2014 |
Patent application number | Description | Published |
20110223753 | Hard Mask Removal for Semiconductor Devices - A method of removing a hard mask during fabrication of semiconductor devices is provided. A protective layer, such as a bottom anti-reflective coating (BARC) layer or other dielectric layer, is formed over structures formed on a substrate, wherein spacers are formed alongside the structures. In an embodiment, the structures are gate electrodes having a hard mask formed thereon and the spacers are spacers formed alongside the gate electrodes. A photoresist layer is formed over the protective layer, and the photoresist layer may be patterned to remove a portion of the photoresist layer over portions of the protective layer. Thereafter, an etch-back process is performed, such that the protective layer adjacent to the spacers remains to substantially protect the spacers. The hard mask is then removed while the protective layer protects the spacers. | 09-15-2011 |
20120248550 | PLASMA DOPING TO REDUCE DIELECTRIC LOSS DURING REMOVAL OF DUMMY LAYERS IN A GATE STRUCTURE - The embodiments of methods and structures disclosed herein provide mechanisms of performing doping an inter-level dielectric film, ILD | 10-04-2012 |
20120322246 | FABRICATION METHODS OF INTEGRATED SEMICONDUCTOR STRUCTURE - A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region. | 12-20-2012 |
20130228871 | PLASMA DOPING TO REDUCE DIELECTRIC LOSS DURING REMOVAL OF DUMMY LAYERS IN A GATE STRUCTURE - A semiconductor device which includes a first gate structure on a substrate and a second gate structure on the substrate is provided. The semiconductor device further includes an inter-level dielectric (ILD) layer on the substrate between the first gate structure and the second gate structure, wherein a top portion of the ILD layer has a different etch selectivity than a bottom portion of the ILD layer. | 09-05-2013 |
20160063166 | Cell Layout and Structure - A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed. | 03-03-2016 |
20160078164 | METHOD OF FORMING LAYOUT DESIGN - A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch. | 03-17-2016 |
20160079162 | SEMICONDUCTOR DEVICE, LAYOUT OF SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having an active area, a gate structure over the active area, a lower conductive layer over and electrically coupled to the active area, and an upper conductive layer over and electrically coupled to the lower conductive layer. The lower conductive layer is at least partially co-elevational with the gate structure. The lower conductive layer includes first and second conductive segments spaced from each other. The upper conductive layer includes a third conductive segment overlapping the first and second conductive segments. The third conductive segment is electrically coupled to the first conductive segment, and electrically isolated from the second conductive segment. | 03-17-2016 |
20160093603 | SYSTEM AND METHOD OF PROCESSING CUTTING LAYOUT AND EXAMPLE SWITCHING CIRCUIT - A method of processing a gate electrode cutting (CUT) layout usable for fabricating an integrated circuit (IC) is disclosed. The method includes determining if a first CUT layout pattern and a second CUT layout pattern are in compliance with a predetermined spatial resolution requirement. If the first CUT layout pattern and the second CUT layout pattern are not in compliance with the predetermined spatial resolution requirement, a merged CUT layout pattern is generated based on the first CUT layout pattern, the second CUT layout pattern, and a stitching layout pattern, and a remedial connecting layout pattern is added to a conductive layer layout. The stitching layout pattern corresponds to a carved-out portion of a third gate electrode structure. The remedial connecting layout pattern corresponds to fabricating a conductive feature electrically connecting two portions of the third gate electrode structure that are separated by the corresponding carved-out portion. | 03-31-2016 |
20160104674 | INTEGRATED CIRCUIT WITH ELONGATED COUPLING - An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width. The length of each of the first lines is greater than the width. The integrated circuit also comprises a second layer on a second level different from the first level. The second layer comprises a set of second lines. The second lines each have a length and a width. The length of each of the second lines is greater than the width. The integrated circuit further comprises a coupling configured to connect at least one first line of the set of first lines with at least one second line of the set of second lines. The coupling has a length and a width. The set of second lines has a pitch measured between the lines of the set of second lines in the first direction. The length of the first coupling is greater than or equal to the pitch. | 04-14-2016 |
20160111370 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature. | 04-21-2016 |
Patent application number | Description | Published |
20140084340 | Contact Structure Of Semiconductor Device - The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer. | 03-27-2014 |
20140124842 | Contact Structure of Semiconductor Device - The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer. | 05-08-2014 |
20140213048 | Method of Making a FinFET Device - A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, fins on the substrate, isolation regions on sides of the fins and dummy gate stacks on the substrate including wrapping a portion of the fin, which is referred to as a gate channel region. The dummy gate stacks is removed to form a gate trench and a gate dielectric layer is deposited in the gate trench. A metal stressor layer (MSL) is conformably deposited on the gate dielectric layer. A capping layer is deposited on the MSL. A thermal treatment is applied to the MSL to achieve a volume expansion. Then the capping layer is removed and a metal gate (MG) is formed on the MSL. | 07-31-2014 |
20140363943 | Contact Structure of Semiconductor Device Priority Claim - The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer. | 12-11-2014 |
20150041854 | FinFET Low Resistivity Contact Formation Method - The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and wherein a surface of the strained material has received a passivation treatment; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; a metal barrier coating an opening of the dielectric layer; and a metal layer filling a coated opening of the dielectric layer. | 02-12-2015 |
20150140763 | Contact Structure of Semiconductor Device - The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer. | 05-21-2015 |
20150221751 | METHOD OF MAKING A FINFET DEVICE - A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, fins on the substrate, isolation regions on sides of the fins and dummy gate stacks on the substrate including wrapping a portion of the fin, which is referred to as a gate channel region. The dummy gate stacks is removed to form a gate trench and a gate dielectric layer is deposited in the gate trench. A metal stressor layer (MSL) is conformably deposited on the gate dielectric layer. A capping layer is deposited on the MSL. A thermal treatment is applied to the MSL to achieve a volume expansion. Then the capping layer is removed and a metal gate (MG) is formed on the MSL. | 08-06-2015 |
20150303106 | Contact Structure of Semiconductor Device - The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer. | 10-22-2015 |
20150303118 | Wrap-Around Contact - Fin structures are formed on a substrate. An isolation region is between the fin structures. The fin structures comprise epitaxial regions extending above the isolation region. Each of the epitaxial regions has a widest mid-region between an upper-surface and an under-surface. A dual-layer etch stop is formed over the fin structures and comprises a first sub-layer and a second sub-layer. The first sub-layer is along the upper- and under-surfaces and the isolation region. The second sub-layer is over the first sub-layer and along the upper-surfaces, and the second sub-layer merges together proximate the widest mid-regions of the epitaxial regions. Portions of the dual-layer etch stop are removed from the upper- and under-surfaces. A dielectric layer is formed on the upper- and under-surfaces. A metal layer is formed on the dielectric layer on the upper-surfaces. A barrier layer is formed on the metal layer and along the under-surfaces. | 10-22-2015 |
Patent application number | Description | Published |
20100188294 | PLANAR ANTENNA - The present invention discloses a planar antenna including a substrate, a ground plane and a feed line. The ground plane is disposed on one side of the substrate. The ground plane includes a hollow portion. The feed line disposed on another side of the substrate and corresponding to the hollow portion for feeding a signal. The present invention also discloses a planar antenna including a substrate, a ground plane and a feed line. The ground plane is disposed on one side of the substrate. The ground plane includes a first hollow portion and a second hollow portion. The feed line is disposed on another side of the substrate and having a first branch feed portion and a second branch feed portion for feeding a signal, and the first branch feed portion and the second branch feed portion are aligned with the first hollow portion and the second hollow portion respectively. | 07-29-2010 |
20110181474 | MINIATURE THREE-DIMENSIONAL ANTENNA - Provided is a miniature three-dimensional antenna. The subject matter is particularly a miniature, low-height, and three-dimensional structure single-frequency antenna. In accordance with the preferred embodiment, the antenna includes a radiation member with extended structure, and the radiation member has a first radiation plane and a non-coplanar second radiation plane. One end extended from the first radiation plane forms a radiation bent member by a bending process. Furthermore, the antenna includes a feed member and a ground member which are the structure extended from the radiation member. In particularly, the first radiation plane, the second radiation plane, the radiation bent member, the feed member, and ground member are not coplanar. The three-dimensional structure is featured to provide the low-height structure, and fortify the antenna structure. Moreover, it is easy to apply to significant number of applications through adjustment of members. | 07-28-2011 |
20130069826 | SWITCHED BEAM SMART ANTENNA APPARATUS AND RELATED WIRELESS COMMUNICATION CIRCUIT - A switched beam smart antenna apparatus is disclosed including: a first, a second, a third, a fourth, a fifth, a sixth, a seventh, and an eighth beam adjusting elements; a first, a second, a third, and a fourth beam control modules; a first, a second, a third, and a fourth radiation strips positioned within an area surrounded by the first to eighth beam adjusting elements; and a radiation strip control module for selecting either the first and second radiation strips or the third and fourth radiation strips to transmit signals. When the first beam control module conducts the first and second beam adjusting elements, the third beam control module does not conduct the fifth and sixth beam adjusting elements. When the second beam control module conducts the third and fourth beam adjusting elements, the fourth beam control module does not conduct the seventh and eighth beam adjusting elements. | 03-21-2013 |
20130099974 | SWITCHED BEAM SMART ANTENNA APPARATUS AND RELATED WIRELESS COMMUNICATION CIRCUIT - A switched beam smart antenna apparatus is disclosed including: a first, a second, a third, and a fourth beam adjusting elements substantially perpendicular to a substrate; a radiation strip positioned within an area surrounded by the first to fourth beam adjusting elements and substantially perpendicular to the substrate; a first beam control module positioned between the first beam adjusting element and the substrate; a second beam control module positioned between the second beam adjusting element and the substrate; a third beam control module positioned between the third beam adjusting element and the substrate; and a fourth beam control module positioned between the fourth beam adjusting element and the substrate. When the first beam control module turns on the first beam adjusting element, at least one of the second through the fourth beam control modules turns off corresponding beam adjusting element. | 04-25-2013 |
20140184459 | DUAL BAND ANTENNA - A dual-band antenna, disposed in a substrate, is provided. The dual-band antenna includes: a feeding part and a slot antenna. The feeding part, disposed on a first side of the substrate, is used for feeding electromagnetic signals with a first resonance frequency and a second resonance frequency, wherein the second resonance frequency is substantially equal to twice the first resonance frequency. The slot antenna includes: a rectangular part with two long edges and two short edges, and a funnel part with a bottom edge, a top edge, and two side edges, wherein the bottom edge is shorter than the top edge, and the two side edges are equal in length substantially, the bottom edge of the funnel part is next to a short edge of the rectangular part, and a center line of the slot antenna corresponds to wavelength of the first frequency. | 07-03-2014 |
20140210673 | DUAL-BAND ANTENNA OF WIRELESS COMMUNICATION APPARATUS - A dual-band antenna of a wireless communication apparatus includes a first radiation part for receiving or transmitting signals at a first frequency band; a second radiation part for generating a coupling effect together with the first radiation part to receive or transmit signals at a second frequency band having a center frequency lower than a center frequency of the first frequency band, wherein the second radiation part comprises multiple radiation sections, and at least one of the multiple radiation sections is positioned on a first plane; a feeding element for coupling with a signal receiving terminal of the wireless communication apparatus; and a shorting element for coupling with a fixed-voltage region of the wireless communication apparatus. The first radiation part does not physically contact with the second radiation part, and at least a portion of the first radiation part is not positioned on the first plane. | 07-31-2014 |
Patent application number | Description | Published |
20150293222 | ULTRASOUND APPARATUS AND ULTRASOUND METHOD FOR BEAMFORMING WITH A PLANE WAVE TRANSMISSION - According to an exemplary embodiment, an ultrasound apparatus for beamforming with a plane wave transmission may comprise a transceiver connected to a transducer array having at least one transducer element, and at least one processor. The transceiver transmits at least one substantially planar ultrasonic wave into a target region at one or more angles relative to the transducer array, and receives one or more signals responsive from the transducer array. The at least one processor applies a fast Fourier transform (FFT) to the one or more signals from each of the at least one transducer element and calculates at least one frequency within a frequency region, and applies an inverse FFT to at least one produced frequency data. | 10-15-2015 |
20150363528 | CIRCUIT ARRANGEMENT FOR MODELING - One or more circuit arrangements and techniques for modeling are provided. In some embodiments, a circuit arrangement includes at least one of a first current source, a second current source, a first diode, a second diode, and a switching component. In some embodiments, the switching component includes a bipolar junction transistor (BJT). In some embodiments, the circuit arrangement is integrated into a metal oxide semiconductor (MOS) device. When the circuit arrangement is integrated into a MOS device, at least one of a substrate current leakage, a junction breakdown, or a diode reverse recovery (DRR) effect is predictable for the MOS device. | 12-17-2015 |