Patent application number | Description | Published |
20100050184 | MULTITASKING PROCESSOR AND TASK SWITCHING METHOD THEREOF - A multitasking processor and a task switching method thereof are provided. The task switching method includes following steps. A first task is executed by the multitasking processor, wherein the first task contains a plurality of switching-point instructions. An interrupt event occurs. Accordingly, the multitasking processor temporarily stops executing the first task and starts to execute a second task. The multitasking processor executes a handling process of the interrupt event and sets a switching flag. After finishing the handling process of the interrupt event, the multitasking processor does not perform task switching but continues to execute the first task, and the multitasking processor only performs task switching to execute the second task when it reaches a switching-point instruction in the first task. | 02-25-2010 |
20130058174 | CONTROLLER AND ACCESS METHOD FOR DDR PSRAM AND OPERATING METHOD THEREOF - A controller for a DDR PSRAM is provided. The controller includes a single rate processing unit, a double rate processing unit and a selector. The signal rate processing unit obtains a single data rate data according to a first data and a first clock. The double rate processing unit obtains a double data rate data according to a second data and a second clock that is two times the frequency of the first clock. The selector selectively provides any of the single data rate data and the double data rate data to the DDR PSRAM via a common bus according to a control signal. | 03-07-2013 |
20130058175 | DDR PSRAM AND DATA WRITING AND READING METHODS THEREOF - A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock, and receives a double data rate data from the controller via the common bus according to a data strobe signal from the controller. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory. | 03-07-2013 |
20140043925 | DDR PSRAM AND DATA WRITING AND READING METHODS THEREOF - A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory. The DDR PSRAM also includes a data transmitter and a data strobe generating unit. The data transmitter obtains data stored in the address of the memory and provides a double data rate data to the controller according to the obtained data, and the data strobe generating unit a data strobe signal to the controller and toggling the data strobe signal in response to the double data rate data. | 02-13-2014 |
Patent application number | Description | Published |
20090091951 | CONTROL CIRCUIT FOR SYNCHRONOUS RECTIFYING AND SOFT SWITCHING OF POWER CONVERTERS - A control circuit for soft switching and synchronous rectifying is provided for power converter. A switching-signal circuit is used for generating drive signals and a pulse signal in response to a leading edge and a trailing edge of a switching signal. The switching signal is developed for regulating the power converter. Drive signals are coupled to switch the power transformer. A propagation delay is developed between drive signals to achieve soft switching of the power converter. An isolation device is coupled to transfer the pulse signal from a primary side of a power transformer to a secondary side of the power transformer. A controller of the integrated synchronous rectifier is coupled to the secondary side of the power transformer for the rectifying operation. The controller is operated to receive the pulse signal for switching on/off the power transistor. The pulse signal is to set or reset a latch circuit of the controller for controlling the power transistor. | 04-09-2009 |
20090109715 | SYNCHRONOUS RECTIFYING FOR SOFT SWITCHING POWER CONVERTERS - An synchronous rectifying apparatus or synchronous rectifying circuit of a soft switching power converter is provided to improve the efficiency. The integrated synchronous rectifying circuit includes: a power transistor connected from a transformer to the output of the power converter for rectifying; a controller having a latch circuit generates a drive signal to control the power transistor in response to a switching signal generated by a winding of the transformer in response to the switching of the transformer. The controller turns off the power transistor when the switching signal is lower than a low-threshold. The power transistor is turned on when the switching signal is higher than a high-threshold. Furthermore, a maximum-on-time circuit provided in the controller is applied to generate a maximum-on-time signal for limiting the maximum on time of the power transistor. | 04-30-2009 |
20090213628 | OFFLINE SYNCHRONOUS RECTIFYING CIRCUIT WITH CURRENT TRANSFORMER FOR SOFT SWITCHING POWER CONVERTERS - A synchronous rectifying circuit of soft switching power converter is provided to improve the efficiency. The integrated synchronous rectifier includes a power transistor connected from a transformer to the output of the power converter for rectifying. A controller having a latch circuit generates a drive signal to control the power transistor in response to a switching-current signal. A current transformer generates the switching-current signal in response to the switching current of the transformer. The controller turns off the power transistor when the switching-current signal is lower than a second threshold. The power transistor is turned on once the switching-current signal is higher than a first threshold. Furthermore, a pulse-width detection circuit generates a pulse signal coupled to disable the drive signal and turn off the power transistor. | 08-27-2009 |
20100014324 | OFFLINE SYNCHRONOUS RECTIFYING CIRCUIT WITH SENSE TRANSISTOR FOR RESONANT SWITCHING POWER CONVERTER - A synchronous rectifying circuit of a resonant switching power converter is provided to improve the efficiency. The synchronous rectifying circuit includes a power transistor and a diode connected to a transformer and an output ground of the power converter for rectifying. A sense transistor is coupled to the power transistor for generating a mirror current correlated to a current of the power transistor. A controller generates a driving signal to control the power transistor in response to a switching-current signal. A current-sense device is coupled to the sense transistor for generating the switching-current signal in response to the mirror current. The controller enables the driving signal to turn on the power transistor once the diode is forwardly biased. The controller generates a reset signal to disable the driving signal and turn off the power transistor once the switching-current signal is lower than a threshold. | 01-21-2010 |
20100124079 | OFFLINE SYNCHRONOUS RECTIFIER WITH CAUSAL CIRCUIT FOR RESONANT SWITCHING POWER CONVERTER - A synchronous rectifier of a resonant switching power converter is provided to improve efficiency. The synchronous rectifier includes a power transistor and a diode connected to a transformer and an output of the resonant switching power converter for ratifications. A controller generates a drive signal to control the power transistor in response to an on signal and an off signal. A causal circuit is developed to generate the off signal in accordance with the on signal. The on signal is enabled once the diode is forward biased. The on signal is coupled to enable the drive signal for switching on the power transistor. The off signal is coupled to disable the drive signal for switching off the power transistor. The off signal is enabled before the on signal is disabled. | 05-20-2010 |
20100172156 | OFFLINE SYNCHRONOUS RECTIFIER CIRCUIT WITH TURNED-ON ARBITER AND PHASE-LOCK FOR SWITCHING POWER CONVERTERS - A synchronous rectifier circuit of a switching power converter is provided and includes first and second power transistors and first and second diodes connected to a transformer and an output of the power converter for rectifying. An arbiter circuit generates a lock signal to prevent the second power transistor from being turned on when the first diode the first power transistor is turned on. A controller generates a drive signal to control the first power transistor according to an on signal and an off signal. A phase-lock circuit generates the off signal according to the on signal. The on signal is enabled once the first diode is forward biased. The one signal enables the drive signal for turning on the first power transistor. The off signal disables the drive signal for turning off the first power transistor. The off signal is enabled before the disabling of the on signal. | 07-08-2010 |
20100201334 | SYNCHRONOUS RECTIFIER HAVING PHASE LOCK CIRCUIT COUPLED TO FEEDBACK LOOP FOR RESONANT POWER CONVERTERS - A synchronous rectifier for a switching power converter is provided and includes a power transistor, a diode, and a control circuit. The power transistor and the diode are coupled to a transformer and an output of the power converter for the rectification. The control circuit generates a drive signal to switch on the power transistor once the diode is forward biased. The control circuit includes a phase-lock circuit. The phase-lock circuit generates an off signal to switch off the power transistor in response to a pulse width of the drive signal. The pulse width of the drive signal is shorter than a turned-on period of the diode. The phase-lock circuit further reduces the pulse width of the drive signal in response to a feedback signal. The feedback signal is correlated to an output load of the power converter. | 08-12-2010 |
20110292702 | METHOD AND APPARATUS TO IMPROVE DYNAMIC RESPONSE OF THE SYNCHRONOUS RECTIFYING FOR RESONANT POWER CONVERTERS - A synchronous rectifying circuit for a switching power converter is provided. The synchronous rectifying circuit includes a power transistor, a diode, and a control circuit. The power transistor and the diode are coupled to a transformer and an output of the power converter for rectification. The control circuit generates a drive signal to switch on the power transistor once the diode is forward biased. The control circuit includes a monitor circuit. The monitor circuit generates a monitor signal an off signal to switch off the power transistor in response to a pulse width of the drive signal for generating an off signal to switch off the power transistor. The monitor circuit further reduces the pulse width of the drive signal in response to a change of a feedback signal. The feedback signal is correlated to an output load of the power converter. | 12-01-2011 |
20110305055 | ADAPTIVE SYNCHRONOUS RECTIFICATION CONTROL METHOD AND APPARATUS - An adaptive synchronous rectification control circuit and a control method are developed. The control circuit comprises an adaptive circuit that generates a reference signal in response to a detection signal of a power converter. A clamped circuit clamps the reference signal at a threshold voltage if the reference signal equals or is greater than the threshold voltage. A switching circuit generates a control signal to control a synchronous switch of the power converter in response to the detection signal and the reference signal. The control method generates the reference signal in response to the detection signal. The reference signal is clamped at the threshold voltage if the reference signal equals or is greater than the threshold voltage. The method further generates the control signal to control the synchronous switch of the power converter in response to the detection signal and the reference signal. | 12-15-2011 |
20120033460 | High-Side Synchronous Rectifier Circuits and Control Circuits for Power Converters - A control circuit for a switching power converter is provided. The control circuit is installed between a secondary side and an output of the power converter and coupled to control a switching device. The control circuit includes a linear predict circuit, a reset circuit, a charge/discharge circuit, and a PWM circuit. The linear predict circuit is coupled to receive a linear predict signal from the secondary side for generating a charging signal. The reset circuit is couple to receive a resetting signal for generating a discharging signal. The charge/discharge circuit is coupled to receive the charging signal and the discharging signal for generating a ramp signal. The PWM circuit is coupled to receive the linear predict signal for enabling a switching signal and receive the ramp signal for resetting the switching signal. | 02-09-2012 |
20130027987 | REGULATION CIRCUIT ASSOCIATED WITH SYNCHRONOUS RECTIFIER PROVIDING CABLE COMPENSATION FOR THE POWER CONVERTER AND METHOD THEREOF - A regulation circuit of a power converter for cable compensation according to the present invention comprises a signal generator generating a compensation signal in accordance with a synchronous rectifying signal. An error amplifier has a reference signal for generating a feedback signal in accordance with an output voltage of the power converter. The compensation signal is coupled to program the reference signal. The feedback signal is coupled to generate a switching signal for regulating an output of the power converter. The regulation circuit of the present invention compensates the output voltage without a shunt resistor to sense the output current of the power converter for reducing power loss. | 01-31-2013 |
20130223111 | DIGITAL CONTROL CIRCUIT FOR RESONANT POWER CONVERTERS - A resonant control circuit for a power converter is provided. The resonant control circuit includes a microcontroller, a switching-signal timer, a first PWM timer, and a signal detection circuit. The microcontroller has a memory circuit, and the memory circuit includes a program memory and a data memory. The switching-signal timer generates a first switching signal coupled to switch a transformer. The first PWM timer generates a PWM signal coupled to control a synchronous rectifying transistor of the power converter for synchronous rectifying. The signal detection circuit is coupled to an output of the power converter for generating a feedback data from a feedback signal. The microcontroller controls the first switching signal by programming the switching-signal timer in accordance with the feedback data. The microcontroller controls the first PWM signal by programming the first PWM timer in response to the first switching signal. | 08-29-2013 |
20140016374 | REGULATION CIRCUIT HAVING OUTPUT CABLE COMPENSATION FOR POWER CONVERTERS AND METHOD THEREOF - A regulation circuit with the output cable compensation is developed for a power converter. It includes an error amplifier for generating a feedback signal in accordance with an output of the power converter. A compensation circuit is coupled to a transformer of the power converter for generating a compensation signal in response to a transformer signal generated by the transformer. The feedback signal is applied to generate a switching signal for switching the transformer and regulating the output of the power converter. The compensation signal is coupled to modulate the feedback signal for compensating a voltage drop of the output cable of the power converter. | 01-16-2014 |
20140118039 | CHARGE PUMP CIRCUITS HAVING FREQUENCY SYNCHRONIZATION WITH SWITCHING FREQUENCY OF POWER CONVERTERS - A control circuit of a power converter is provided. The control circuit includes a switching circuit and a charge pump circuit. The switching circuit generates a switching signal for controlling the power converter. The charge pump circuit includes an oscillator for generating an oscillation signal synchronized with the switching signal. The oscillation signal is coupled to control a switch of the charge pump circuit for generating a voltage source. | 05-01-2014 |
20140192565 | CIRCUIT WITH SYNCHRONOUS RECTIFIER FOR CONTROLLING PROGRAMMABLE POWER CONVERTER - A control circuit of a power converter and a method for controlling the power converter are provided. The control circuit of the power converter comprises a switching circuit and a temperature-sensing device. The switching circuit generates a switching signal in response to a feedback signal, and the switching circuit generates a current-sensing signal for regulating an output of the power converter. The temperature-sensing device generates a temperature signal in response to temperature of the temperature-sensing device. | 07-10-2014 |
20140198535 | METHOD AND APPARATUS FOR CONTROLLING PROGRAMMABLE POWER CONVERTER WITH LOW STANDBY POWER LOSS - Method and apparatus for controlling a programmable power converter are provided. The method and apparatus generate a first power source and a second power source. The voltage level of the second power source is lower than the voltage level of the first power source. The first power source and the second power source provide a power supply for a control circuit. The control circuit will use the first power source as its power supply when the first power source is low. The control circuit will use the second power source as its power supply for saving the power when the first power source is high. | 07-17-2014 |
20140268914 | METHOD OF CONTROLLING SYNCHRONOUS RECTIFIER FOR POWER CONVERTER, CONTROL CIRCUIT, AND POWER CONVERTER THEREOF - A method for controlling a synchronous rectifier for a power converter, a control circuit, and a power converter thereof are provided. The method comprises the following steps: turning on a transistor by a rectifier; generating a switching-period signal in accordance with a period of a voltage-sensing signal; generating a turn-on-period signal in accordance with a turned-on period of the rectifier; generating a first disabling signal responding to the switching-period signal; and generating a second disabling signal in response to the turn-on-period signal. The transistor is turned off in response to the first disabling signal and the second disabling signal, and the voltage-sensing signal is related to the switching waveform of a transformer. | 09-18-2014 |
20140372776 | METHOD AND APPARATUS FOR SELECTING THE OUTPUT OF PROGRAMMABLE POWER ADAPTER - An apparatus of programming an output of a programmable power adapter according to the present invention comprises a control circuit. The method according to the present invention sends a signal to a device. A resistor is coupled to the signal to determine the level of the signal. The resistor is installed in the device. The method according to the present invention checks the level of the signal in the programmable power adapter and determines an output voltage of the programmable power adapter in accordance with the level of the signal. The output voltage of the programmable power adapter is coupled to the device to provide a power for a load of the device. | 12-18-2014 |
20150049523 | METHOD FOR CONTROLLING SYNCHRONOUS RECTIFIER OF POWER CONVERTER AND CONTROL CIRCUIT USING THE SAME - The invention discloses a method for controlling a synchronous rectifier of a power converter and a control circuit using the same. The method includes the following steps. A control signal is generated to control a synchronous rectification transistor in response to an on-time of a switching signal, a level of a transformer voltage and an output voltage of the power converter. The switching signal is used for switching a transformer. The control signal is generated once the switching signal is turned off. A transformer signal is related to an input voltage of the power converter. The control signal is generated when the on-time of the switching signal is longer than a first time threshold. | 02-19-2015 |
20150062972 | SYNCHRONOUS RECTIFIER CONTROL CIRCUITS OF POWER CONVERTERS - A synchronous rectifying control circuit of a power converter is provided. The synchronous rectifying control circuit comprises a synchronous rectifying driver, a charge pump capacitor, and a capacitor. The synchronous rectifying driver is coupled to a transformer for generating a control signal to switch a transistor. The charge pump capacitor is coupled to a power source for generating a charge pump voltage. The capacitor is coupled to store the charge pump voltage. The transistor is coupled to the transformer and operated as a synchronous rectifier. The charge pump voltage is coupled to guarantee a sufficient driving capability for the control signal. | 03-05-2015 |
Patent application number | Description | Published |
20080303966 | PIXEL STRUCTURE - A pixel structure including a substrate, a scan line, a data line, a first and a second switching device, a first and a second pixel electrode, a first and a second bended pixel electrode, a first and a second connecting conductive layer, and a first and a second common line is provided. The scan line and data line demarcate a first and a second areas on the substrate, and the scan line is located between the two areas. The first and second switching devices are electrically connected to the scan line and the data line and are also electrically connected to the first and second pixel electrodes on the first and second areas respectively. The first and second bended pixel electrodes on the second and first areas are electrically connected to the first and second pixel electrodes through the first and second connecting conductive layers on the scan line respectively. | 12-11-2008 |
20080303970 | PIXEL STRUCTURE - A pixel structure includes a gate, a source, a first drain, a second drain, a third drain, a first pixel electrode, a second pixel electrode, a scan line and a data line. The gate, the source and the first drain form a first thin film transistor. The gate, the source and the second drain form a second thin film transistor. The gate, the second drain and the third drain form a sub-thin film transistor (sub-TFT). Additionally, the first pixel electrode is electrically connected to the first drain, and the second drain extends to a portion between the second pixel electrode and the substrate such that a capacitor-coupling electrode is formed. Moreover, the second pixel electrode is electrically connected to the third drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source. | 12-11-2008 |
20100141861 | PIXEL STRUCTURE AND REPAIR METHOD THEREOF - A pixel structure is provided. The pixel structure includes a scan line, a gate, a first dielectric layer, a channel layer, a source, a drain, a data line, a second dielectric layer, and a pixel electrode. The gate is electrically connected to the scan line and has a first notch. The first dielectric layer covers the scan line and the gate. The channel layer is disposed on the first dielectric layer over the gate and exposed by the first notch. The source and the drain are disposed on the channel layer. Part of the drain is located over the first notch. The data line is disposed on the first dielectric layer and electrically connected to the source. The second dielectric layer covers the source, the drain and the data line. The pixel electrode is disposed on the second dielectric layer and electrically connected to the drain. | 06-10-2010 |
20100237350 | PIXEL STRUCTURE - A pixel structure suitable for being disposed on a substrate includes a thin film transistor (TFT), a first pixel electrode, a second pixel electrode, a scan line and a data line. The TFT disposed on the substrate includes a gate, a source, a first drain and a second drain. A main TFT is formed by the gate, the source and the first drain. A sub-thin film transistor (sub-TFT) is formed by the gate, the first drain and the second drain. The first pixel electrode is electrically connected to the first drain, and a portion of the first drain extends between the second pixel electrode and the substrate to form capacitor-coupling electrode. The second pixel electrode is electrically connected to the second drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source. | 09-23-2010 |
Patent application number | Description | Published |
20080217693 | Structure to improve MOS transistor on-breakdown voltage and method of making the same - A novel MOS transistor structure and methods of making the same are provided. The structure includes a MOS transistor formed on a semiconductor substrate of a first conductivity type with a plug region of first conductivity type formed in the drain extension region of second conductivity type (in the case of a high voltage MOS transistor) or in the lightly doped drain (LDD) region of second conductivity type (in the case of a low voltage MOS transistor). Such structure leads to higher on-breakdown voltage. The inventive principle applies to MOS transistors formed on bulky semiconductor substrate and MOS transistors formed in silicon-on-insulator configuration. | 09-11-2008 |
20150041891 | Ultra-High Voltage Laterally-Diffused MOS Devices and Methods of Forming the Same - Embodiments for the present disclosure include a semiconductor device, an ultra-high voltage (UHV) laterally-diffused metal-oxide-semiconductor (LDMOS) transistor, and methods of forming the same. An embodiment includes a first well region of a first conductivity type in a top surface of a substrate, and a second well region of a second conductivity type in the top surface of the substrate. The second well region laterally separated from the first well region by a portion of the substrate. The embodiment further includes a third region of the second conductivity type in the first well region, and a first field oxide region in the first well region, a second field oxide region in the second well region, the second field oxide region having a second bottom surface, and the first field oxide region having a first bottom surface lower than the second bottom surface and on and directly contacting the third region. | 02-12-2015 |
20150187872 | SUPER JUNCTION WITH AN ANGLED TRENCH, TRANSISTOR HAVING THE SUPER JUNCTION AND METHOD OF MAKING THE SAME - A super junction includes a substrate and an epitaxial layer over the substrate, the epitaxial layer having a first dopant type. The super junction further includes an angled trench in the epitaxial layer, the angled trench having sidewalls disposed at an angle ranging from about 85-degrees to about 89-degrees with respect to a top surface of the epitaxial layer. The super junction further includes a doped body in the epitaxial layer surrounding the angled trench, the doped body having a second dopant type, the second dopant type opposite that of the first dopant type. | 07-02-2015 |
Patent application number | Description | Published |
20120249115 | BANDGAP REFERENCE CIRCUIT - A bandgap reference circuit includes a modulator, an amplifier, a demodulator, a closed feedback loop and an output circuit. The modulator is utilized for modulating an input signal to generate a modulated input signal. The amplifier is utilized for amplifying the modulated input signal to generate an amplified modulated input signal. The demodulator is utilized for demodulating the amplified modulated input signal to generate a demodulated signal. The closed feedback loop is coupled between an output terminal of the demodulator and an input terminal of the modulator. The output circuit is utilized for generating an output current according to the demodulated signal, where the output current is a constant current insensitive to fluctuations in temperature. | 10-04-2012 |
20120250721 | TEMPERATURE MEASUREMENT CIRCUIT AND TEMPERATURE MEASUREMENT METHOD - A temperature measurement circuit includes a sensing unit and a temperature translation unit. The sensing unit is arranged for generating a positive temperature coefficient characteristic and a negative temperature coefficient characteristic according to a temperature. The temperature translation unit is coupled to the sensing unit, and is arranged for generating a measured temperature according to the positive temperature coefficient characteristic and the negative temperature coefficient characteristic. | 10-04-2012 |
20140176355 | METHOD OF DYNAMIC ELEMENT MATCHING AND AN APPARATUS THEREOF - A method to reduce the integral non-linearity (INL) of a digital-to-analog converter (DAC) and a DAC implementing said method are disclosed. The method in this invention is a pseudo dynamic element matching (PDEM) method. Compared with a prior art, the method of this invention provides a better performance in glitch. Compared with another prior art, the method of this invention also guarantees that DEM will not fail even if the input digital code remains constant. | 06-26-2014 |
20150109159 | ANALOG TO DIGITAL CONVERTER - An analog to digital converter is disclosed herein. The analog to digital converter includes a bit conversion module and a control module. The bit conversion module is configured to generate a quantization output in accordance with an input signal. The control module is configured to control the bit conversion module, so as to make the bit conversion module operate in one of a sigma delta mode and a successive approximation mode. | 04-23-2015 |
Patent application number | Description | Published |
20110302429 | SERVER RACK SYSTEM - A rack system for a server includes a number of server units, which includes first to the third sets of server units, voltage converter, first to third power supply circuits. The voltage converter receives and converters a three-phase alternating current (AC) power signal to provide first to third single-phase power signals. The first to the third sets of power supply circuits respectively provides first to third direct current (DC) power signals according to the first to the third single-phase power signals. The first set to the third set of server units is respectively powered by first to the third DC power signals or respectively powered by first part, second part, and third part of the first to the third DC power signals. | 12-08-2011 |
20120327591 | RACK SERVER SYSTEM - A rack server system includes a number of server units and a rack. The rack server includes a back plane, a control module, a fan module and a power supply module. The back plane includes a number of slots, via which the server units are respectively connected to the back plane. The fan module is connected to the control module, and dissipates heat generated by the server units under the control of the control module. The power supply module is connected to the control module, and powers the server units under the control of the control module. | 12-27-2012 |
20130030735 | RACK SERVER SYSTEM AND CONTROL METHOD THEREOF - A rack server system and a control method thereof are provided. The rack server system establishes a communication link for communicating with a battery backup unit. The battery backup unit is connected to a power input port of the rack server system, and includes a number of battery modules connected with each other in parallel. The rack server system controls the battery backup unit to perform validity test on a first battery module during a first period and to perform validity test on a second battery module during a second period, wherein the first period and the second period are not overlapped with each other. | 01-31-2013 |
20130031381 | RACK SERVER SYSTEM - A rack server system including at least one server and a battery backup unit (BBU) is provided. A power supplier is coupled to the server for converting an input voltage into a first output voltage when the input voltage is normal and for providing the first output voltage to the server. The BBU is coupled to the server and the power supplier for detecting the first output voltage outputted from the power supplier and for providing a second output voltage to the server when the input voltage and/or the first output voltage are abnormal. | 01-31-2013 |
20130031382 | RACK SERVER SYSTEM AND OPERATION METHOD APPLICABLE THERETO - A rack server system and an operating method applicable thereto are provided. The rack server system includes a battery backup unit (BBU) and at least one server. The operating method includes: communicating the server and the BBU with each other; the BBU providing a status information and a previous self-discharging test information to the server for the server to judge a status of the BBU; and providing power from the BBU to the server and adjusting a loading of the server according to the status information of the BBU when an input power is interrupted. | 01-31-2013 |
20130039001 | SERVER SYSTEM - A server system includes a rack, a power supply module, a switch, and a plurality of servers. The rack can be divided into a plurality of rack units. The rack units are parallel to each other and vertically arranged. The power supply module and the switch are disposed in close proximity to each other in at least one of the rack units. The power supply is adjacent to the rear side of the rack. The switch is adjacent to the front side of the rack. Each of the servers is disposed in one of the other rack units and electrically connected to the power supply module and the switch. | 02-14-2013 |
20130227309 | SERVER SYSTEM - A server system is disclosed. The server system comprises a motherboard and a server power system. The server power system comprises a power transmission interface, a power supply, a battery backup unit (BBU) and a signal transmission interface. The power supply converts an AC power into a DC power and then outputs the DC power to the motherboard via the power transmission interface. The BBU provides parallel or redundant power to the motherboard via the power transmission interface. The BBU and the power supply have the same size. The signal transmission interface is electrically connected to the motherboard, the power supply and the BBU. | 08-29-2013 |
20130227310 | SERVER POWER SYSTEM - A power server system is disclosed. The power server system comprises a power transmission interface, a power supply and a battery backup unit (BBU). The power supply converts an AC power into a DC power and outputs the DC power to the power transmission interface. After the AC power is disconnected, the power supply continues outputting the DC power in a holding period having an arising period and a current sharing period. The BBU outputs a redundant power to the power transmission interface before the power supply stop outputting the DC power. The BBU boosts the voltage level of the redundant power in the arising period, and controls the voltage level of the redundant power to be the same with that of the DC power in the current sharing period, so that the battery output inrush current is reduced and the battery life is extended. | 08-29-2013 |
20140281646 | POWER MANAGEMENT METHOD FOR SERVER SYSTEM - A power management method for a server system is provided. At least any one of a power status indication signal and an alert signal from a power supply is detected to judge whether an input voltage is normal. If it is judged that the input voltage is abnormal, a motherboard sends the power status indication signal to a battery backup unit (BBU) to inform the BBU to supply power to the motherboard. If it is judged that the input voltage is abnormal, the motherboard lowers its loading. | 09-18-2014 |
20150039918 | RACK SERVER SYSTEM AND OPERATION METHOD APPLICABLE THERETO - A rack server system and an operating method applicable thereto are provided. The rack server system includes a battery backup unit (BBU) and at least one server. The operating method includes: communicating the server and the BBU with each other; the BBU providing a status information and a previous self-discharging test information to the server for the server to judge a status of the BBU; and providing power from the BBU to the server and adjusting a loading of the server according to the status information of the BBU when an input power is interrupted. | 02-05-2015 |
Patent application number | Description | Published |
20090037166 | AUDIO ENCODING METHOD WITH FUNCTION OF ACCELERATING A QUANTIZATION ITERATIVE LOOP PROCESS - An audio encoding method previously estimates better initial iterative values of global-gain and scalefactor for avoiding heavy calculation. The estimating process of the encoding method includes calculating the bit allocation of one frequency sample based on a sampling rate, a bit rate, and the number of audio channels according to an input frame, and the psychoacoustic model, searching one frequency sample having the greatest sample energy in each of a plurality of scalefactor bands, quantizing the frequency sample to comply with the bit allocation and to generate a corresponding scalefactor, searching a maximum scalefactor of all scalefactor bands corresponding to the input frame, and setting initial values of scalefactors and an initial value of global-gain for the quantization iterative loop process according to the corresponding scalefactor and the maximum scalefactor. | 02-05-2009 |
20090103752 | DEVICE AND METHOD FOR AUTOMATICALLY ADJUSTING GAIN - A device and method are provided for automatically adjusting gain, including a conversion module for converting an audio time-domain signal to an audio frequency-domain signal, an analysis module for analyzing the audio frequency-domain signal in accordance with an equal-loudness level contour of human hearing so as to generate strength weightings and generating a signal strength in accordance with the weightings, a calculation module for calculating a gain by analysis of the audio frequency-domain signal when the signal strength falls outside a default range, and a control module for generating an audio output signal in accordance with the gain and the audio time-domain signal. | 04-23-2009 |
20090257335 | AUDIO SIGNAL PROCESSING METHOD - An audio signal processing method includes the steps of: dividing an audio signal data stream into a plurality of selection segments; determining a target segment in the audio signal data stream, the target segment including a splice point for splicing a splice segment thereto; selecting one of the selection segments as the splice segment according to at least one parameter of the target segment; and processing the target segment and the splice segment to splice the splice segment to the target segment, and outputting a processed segment. | 10-15-2009 |