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| 20090091951 | CONTROL CIRCUIT FOR SYNCHRONOUS RECTIFYING AND SOFT SWITCHING OF POWER CONVERTERS - A control circuit for soft switching and synchronous rectifying is provided for power converter. A switching-signal circuit is used for generating drive signals and a pulse signal in response to a leading edge and a trailing edge of a switching signal. The switching signal is developed for regulating the power converter. Drive signals are coupled to switch the power transformer. A propagation delay is developed between drive signals to achieve soft switching of the power converter. An isolation device is coupled to transfer the pulse signal from a primary side of a power transformer to a secondary side of the power transformer. A controller of the integrated synchronous rectifier is coupled to the secondary side of the power transformer for the rectifying operation. The controller is operated to receive the pulse signal for switching on/off the power transistor. The pulse signal is to set or reset a latch circuit of the controller for controlling the power transistor. | 04-09-2009 |
| 20090109715 | SYNCHRONOUS RECTIFYING FOR SOFT SWITCHING POWER CONVERTERS - An synchronous rectifying apparatus or synchronous rectifying circuit of a soft switching power converter is provided to improve the efficiency. The integrated synchronous rectifying circuit includes: a power transistor connected from a transformer to the output of the power converter for rectifying; a controller having a latch circuit generates a drive signal to control the power transistor in response to a switching signal generated by a winding of the transformer in response to the switching of the transformer. The controller turns off the power transistor when the switching signal is lower than a low-threshold. The power transistor is turned on when the switching signal is higher than a high-threshold. Furthermore, a maximum-on-time circuit provided in the controller is applied to generate a maximum-on-time signal for limiting the maximum on time of the power transistor. | 04-30-2009 |
| 20090213628 | OFFLINE SYNCHRONOUS RECTIFYING CIRCUIT WITH CURRENT TRANSFORMER FOR SOFT SWITCHING POWER CONVERTERS - A synchronous rectifying circuit of soft switching power converter is provided to improve the efficiency. The integrated synchronous rectifier includes a power transistor connected from a transformer to the output of the power converter for rectifying. A controller having a latch circuit generates a drive signal to control the power transistor in response to a switching-current signal. A current transformer generates the switching-current signal in response to the switching current of the transformer. The controller turns off the power transistor when the switching-current signal is lower than a second threshold. The power transistor is turned on once the switching-current signal is higher than a first threshold. Furthermore, a pulse-width detection circuit generates a pulse signal coupled to disable the drive signal and turn off the power transistor. | 08-27-2009 |
| 20100014324 | OFFLINE SYNCHRONOUS RECTIFYING CIRCUIT WITH SENSE TRANSISTOR FOR RESONANT SWITCHING POWER CONVERTER - A synchronous rectifying circuit of a resonant switching power converter is provided to improve the efficiency. The synchronous rectifying circuit includes a power transistor and a diode connected to a transformer and an output ground of the power converter for rectifying. A sense transistor is coupled to the power transistor for generating a mirror current correlated to a current of the power transistor. A controller generates a driving signal to control the power transistor in response to a switching-current signal. A current-sense device is coupled to the sense transistor for generating the switching-current signal in response to the mirror current. The controller enables the driving signal to turn on the power transistor once the diode is forwardly biased. The controller generates a reset signal to disable the driving signal and turn off the power transistor once the switching-current signal is lower than a threshold. | 01-21-2010 |
| 20100124079 | OFFLINE SYNCHRONOUS RECTIFIER WITH CAUSAL CIRCUIT FOR RESONANT SWITCHING POWER CONVERTER - A synchronous rectifier of a resonant switching power converter is provided to improve efficiency. The synchronous rectifier includes a power transistor and a diode connected to a transformer and an output of the resonant switching power converter for ratifications. A controller generates a drive signal to control the power transistor in response to an on signal and an off signal. A causal circuit is developed to generate the off signal in accordance with the on signal. The on signal is enabled once the diode is forward biased. The on signal is coupled to enable the drive signal for switching on the power transistor. The off signal is coupled to disable the drive signal for switching off the power transistor. The off signal is enabled before the on signal is disabled. | 05-20-2010 |
| 20100172156 | OFFLINE SYNCHRONOUS RECTIFIER CIRCUIT WITH TURNED-ON ARBITER AND PHASE-LOCK FOR SWITCHING POWER CONVERTERS - A synchronous rectifier circuit of a switching power converter is provided and includes first and second power transistors and first and second diodes connected to a transformer and an output of the power converter for rectifying. An arbiter circuit generates a lock signal to prevent the second power transistor from being turned on when the first diode the first power transistor is turned on. A controller generates a drive signal to control the first power transistor according to an on signal and an off signal. A phase-lock circuit generates the off signal according to the on signal. The on signal is enabled once the first diode is forward biased. The one signal enables the drive signal for turning on the first power transistor. The off signal disables the drive signal for turning off the first power transistor. The off signal is enabled before the disabling of the on signal. | 07-08-2010 |
| 20100201334 | SYNCHRONOUS RECTIFIER HAVING PHASE LOCK CIRCUIT COUPLED TO FEEDBACK LOOP FOR RESONANT POWER CONVERTERS - A synchronous rectifier for a switching power converter is provided and includes a power transistor, a diode, and a control circuit. The power transistor and the diode are coupled to a transformer and an output of the power converter for the rectification. The control circuit generates a drive signal to switch on the power transistor once the diode is forward biased. The control circuit includes a phase-lock circuit. The phase-lock circuit generates an off signal to switch off the power transistor in response to a pulse width of the drive signal. The pulse width of the drive signal is shorter than a turned-on period of the diode. The phase-lock circuit further reduces the pulse width of the drive signal in response to a feedback signal. The feedback signal is correlated to an output load of the power converter. | 08-12-2010 |
| 20110292702 | METHOD AND APPARATUS TO IMPROVE DYNAMIC RESPONSE OF THE SYNCHRONOUS RECTIFYING FOR RESONANT POWER CONVERTERS - A synchronous rectifying circuit for a switching power converter is provided. The synchronous rectifying circuit includes a power transistor, a diode, and a control circuit. The power transistor and the diode are coupled to a transformer and an output of the power converter for rectification. The control circuit generates a drive signal to switch on the power transistor once the diode is forward biased. The control circuit includes a monitor circuit. The monitor circuit generates a monitor signal an off signal to switch off the power transistor in response to a pulse width of the drive signal for generating an off signal to switch off the power transistor. The monitor circuit further reduces the pulse width of the drive signal in response to a change of a feedback signal. The feedback signal is correlated to an output load of the power converter. | 12-01-2011 |
| 20110305055 | ADAPTIVE SYNCHRONOUS RECTIFICATION CONTROL METHOD AND APPARATUS - An adaptive synchronous rectification control circuit and a control method are developed. The control circuit comprises an adaptive circuit that generates a reference signal in response to a detection signal of a power converter. A clamped circuit clamps the reference signal at a threshold voltage if the reference signal equals or is greater than the threshold voltage. A switching circuit generates a control signal to control a synchronous switch of the power converter in response to the detection signal and the reference signal. The control method generates the reference signal in response to the detection signal. The reference signal is clamped at the threshold voltage if the reference signal equals or is greater than the threshold voltage. The method further generates the control signal to control the synchronous switch of the power converter in response to the detection signal and the reference signal. | 12-15-2011 |
| 20120033460 | High-Side Synchronous Rectifier Circuits and Control Circuits for Power Converters - A control circuit for a switching power converter is provided. The control circuit is installed between a secondary side and an output of the power converter and coupled to control a switching device. The control circuit includes a linear predict circuit, a reset circuit, a charge/discharge circuit, and a PWM circuit. The linear predict circuit is coupled to receive a linear predict signal from the secondary side for generating a charging signal. The reset circuit is couple to receive a resetting signal for generating a discharging signal. The charge/discharge circuit is coupled to receive the charging signal and the discharging signal for generating a ramp signal. The PWM circuit is coupled to receive the linear predict signal for enabling a switching signal and receive the ramp signal for resetting the switching signal. | 02-09-2012 |
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| 20080303966 | PIXEL STRUCTURE - A pixel structure including a substrate, a scan line, a data line, a first and a second switching device, a first and a second pixel electrode, a first and a second bended pixel electrode, a first and a second connecting conductive layer, and a first and a second common line is provided. The scan line and data line demarcate a first and a second areas on the substrate, and the scan line is located between the two areas. The first and second switching devices are electrically connected to the scan line and the data line and are also electrically connected to the first and second pixel electrodes on the first and second areas respectively. The first and second bended pixel electrodes on the second and first areas are electrically connected to the first and second pixel electrodes through the first and second connecting conductive layers on the scan line respectively. | 12-11-2008 |
| 20080303970 | PIXEL STRUCTURE - A pixel structure includes a gate, a source, a first drain, a second drain, a third drain, a first pixel electrode, a second pixel electrode, a scan line and a data line. The gate, the source and the first drain form a first thin film transistor. The gate, the source and the second drain form a second thin film transistor. The gate, the second drain and the third drain form a sub-thin film transistor (sub-TFT). Additionally, the first pixel electrode is electrically connected to the first drain, and the second drain extends to a portion between the second pixel electrode and the substrate such that a capacitor-coupling electrode is formed. Moreover, the second pixel electrode is electrically connected to the third drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source. | 12-11-2008 |
| 20100141861 | PIXEL STRUCTURE AND REPAIR METHOD THEREOF - A pixel structure is provided. The pixel structure includes a scan line, a gate, a first dielectric layer, a channel layer, a source, a drain, a data line, a second dielectric layer, and a pixel electrode. The gate is electrically connected to the scan line and has a first notch. The first dielectric layer covers the scan line and the gate. The channel layer is disposed on the first dielectric layer over the gate and exposed by the first notch. The source and the drain are disposed on the channel layer. Part of the drain is located over the first notch. The data line is disposed on the first dielectric layer and electrically connected to the source. The second dielectric layer covers the source, the drain and the data line. The pixel electrode is disposed on the second dielectric layer and electrically connected to the drain. | 06-10-2010 |
| 20100237350 | PIXEL STRUCTURE - A pixel structure suitable for being disposed on a substrate includes a thin film transistor (TFT), a first pixel electrode, a second pixel electrode, a scan line and a data line. The TFT disposed on the substrate includes a gate, a source, a first drain and a second drain. A main TFT is formed by the gate, the source and the first drain. A sub-thin film transistor (sub-TFT) is formed by the gate, the first drain and the second drain. The first pixel electrode is electrically connected to the first drain, and a portion of the first drain extends between the second pixel electrode and the substrate to form capacitor-coupling electrode. The second pixel electrode is electrically connected to the second drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source. | 09-23-2010 |
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| 20090037166 | AUDIO ENCODING METHOD WITH FUNCTION OF ACCELERATING A QUANTIZATION ITERATIVE LOOP PROCESS - An audio encoding method previously estimates better initial iterative values of global-gain and scalefactor for avoiding heavy calculation. The estimating process of the encoding method includes calculating the bit allocation of one frequency sample based on a sampling rate, a bit rate, and the number of audio channels according to an input frame, and the psychoacoustic model, searching one frequency sample having the greatest sample energy in each of a plurality of scalefactor bands, quantizing the frequency sample to comply with the bit allocation and to generate a corresponding scalefactor, searching a maximum scalefactor of all scalefactor bands corresponding to the input frame, and setting initial values of scalefactors and an initial value of global-gain for the quantization iterative loop process according to the corresponding scalefactor and the maximum scalefactor. | 02-05-2009 |
| 20090103752 | DEVICE AND METHOD FOR AUTOMATICALLY ADJUSTING GAIN - A device and method are provided for automatically adjusting gain, including a conversion module for converting an audio time-domain signal to an audio frequency-domain signal, an analysis module for analyzing the audio frequency-domain signal in accordance with an equal-loudness level contour of human hearing so as to generate strength weightings and generating a signal strength in accordance with the weightings, a calculation module for calculating a gain by analysis of the audio frequency-domain signal when the signal strength falls outside a default range, and a control module for generating an audio output signal in accordance with the gain and the audio time-domain signal. | 04-23-2009 |
| 20090257335 | AUDIO SIGNAL PROCESSING METHOD - An audio signal processing method includes the steps of: dividing an audio signal data stream into a plurality of selection segments; determining a target segment in the audio signal data stream, the target segment including a splice point for splicing a splice segment thereto; selecting one of the selection segments as the splice segment according to at least one parameter of the target segment; and processing the target segment and the splice segment to splice the splice segment to the target segment, and outputting a processed segment. | 10-15-2009 |
