Patent application number | Description | Published |
20130062115 | OUTDOOR CONTROL CABLE - An outdoor control cable includes a cable, a ground terminal, other terminals, and a connector. The cable includes an insulating coating, power lines enclosed by an insulating layer, signal lines enclosed by the insulating layer, and a metal shield. The power lines and the signal lines are enclosed by the insulating coating. The signal lines are further enclosed by the metal shield. The ground terminal is electrically connected to the metal shield. The other terminals are electrically connected to the power lines and the signal lines. The connector includes a casing, a jack, and the ground terminal and other terminals which are protruded and exposed from the jack. Hence, the outdoor control cable has both power lines and signal lines. The metal shield blocks electromagnetic interference from the power lines. | 03-14-2013 |
20130065431 | INNER WIRE FOR INVERTER - An inner wire capable of power integration and power division and adapted for use with an inverter having a casing and a circuit board includes a female connector and a male connector. The female and male connectors are each disposed in the casing and each include power lines, at least two signal lines, and a ground line. The power lines each have one end electrically connected to power connectors in pairs and the other end to power terminals respectively. The signal lines have one end electrically connected to two signal connectors respectively and the other end to signal terminals. The ground lines have one end electrically connected to ground connectors and the other end to ground terminals. The power terminals, signal terminals, and ground terminals are disposed in the male and female connectors. The signal connectors, ground connectors, and power connectors are electrically connected to the circuit board. | 03-14-2013 |
Patent application number | Description | Published |
20130216177 | METHOD OF FABRICATION POLYMER WAVEGUIDE - A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region. | 08-22-2013 |
20130223789 | OPTICAL BENCH ON SUBSTRATE - An optical bench on substrate includes a substrate and a trench formed inside the substrate and having a sloping side. A reflector layer is formed over the sloping side. An optical component is mounted over the substrate. The reflector layer is configured to reflect an electromagnetic wave to or from the optical component. | 08-29-2013 |
20140206110 | Etchant and Etching Process - A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration. Then, based upon such measurement, a makeup amount of the components may be added be a makeup unit to the etching solution to control the concentration of the components within the etching system. | 07-24-2014 |
20140206191 | Etchant and Etching Process - A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide. | 07-24-2014 |
20150016793 | Waveguide Structure - A waveguide structure includes a bottom dielectric layer, a core layer disposed over the bottom dielectric layer, an etch stop layer disposed over the core layer, and a cladding layer or a buffer layer disposed over the etch stop layer. The waveguide structure is configured to guide a light signal through different geography, such as straight, taper, turning, grating and tight coupling sections. | 01-15-2015 |
20150061126 | MANUFACTURE INCLUDING SUBSTRATE AND PACKAGE STRUCTURE OF OPTICAL CHIP - A manufacture includes a package structure, a first substrate, and a conductive member of a same material. The package structure includes a chip comprising a conductive pad, a conductive structure over the chip, and a passivation layer over the conductive structure. The passivation layer has an opening defined therein, and the opening exposes a portion of a planar portion of the conductive structure. The first substrate includes a first surface defining a first reference plane and a second surface defining a second reference plane. The conductive member extends across the first reference plane and the second reference plane and into the opening. The conductive member is electrically coupled to the exposed portion of the planar portion. | 03-05-2015 |
20150061137 | PACKAGE AND METHOD FOR INTEGRATION OF HETEROGENEOUS INTEGRATED CIRCUITS - A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip. | 03-05-2015 |
20150145082 | BACKSIDE-ILLUMINATED PHOTODETECTOR STRUCTURE AND METHOD OF MAKING THE SAME - A backside-illuminated photodetector structure comprising a first reflecting region, a second reflecting region and a semiconductor region. The semiconductor region is between the first reflecting region and the second reflecting region. The semiconductor region comprises a first doped region and a second doped region. | 05-28-2015 |
20150146275 | ELECTRO-OPTIC MODULATOR DEVICE AND METHOD OF MAKING THE SAME - An electro-optic modulator including a semiconductor region, a first reflecting region over the semiconductor region and an anti-reflecting region on an opposite surface of the semiconductor region from the first reflecting layer. The semiconductor region includes a first doped region and a second doped region. | 05-28-2015 |
20150155260 | Temporary Bonding Scheme - A method includes filling a trench formed in a first integrated circuit carrier with temporary bonding material to form a temporary bonding layer. At least one chip is bonded over the temporary bonding layer. | 06-04-2015 |
20150234137 | OPTICAL BENCH ON SUBSTRATE AND METHOD OF MAKING THE SAME - An optical bench includes a substrate having a trench therein, and a light emitting device within the trench. The optical bench further includes a light receiving device optically connected to the light emitting device. The optical bench further includes at least one active circuit electrically connected to the light emitting device. The optical bench further includes a waveguide in the trench, wherein the waveguide is optically between the light emitting device and the light receiving device. The optical bench further includes an optically transparent material between the light emitting device and the waveguide. | 08-20-2015 |
20150253500 | Method of Fabrication Polymer Waveguide - A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region. | 09-10-2015 |
20150287705 | APPARATUS AND PACKAGE STRUCTURE OF OPTICAL CHIP - An apparatus includes a package structure. The package structure includes a chip, a conductive structure over the chip, a molding structure surrounding and underneath the chip, and a first passivation layer over the conductive structure. The chip includes an optical component and a chip conductive pad. The conductive structure is electrically coupled to the chip conductive pad. The conductive structure has a planar portion substantially in parallel with an upper surface of the chip. The first passivation layer has a first opening defined therein. The first opening exposes a portion of the planar portion. The package structure is configured to receive an electrical coupling through the first opening in the first passivation layer. | 10-08-2015 |
Patent application number | Description | Published |
20130313882 | FOLDABLE LEG REST - A foldable leg rest has a slide base, a first folding assembly, a second folding assembly, a first stage drive mechanism and a second stage drive mechanism. The slide base has a slide frame. The first folding assembly has a first frame pivotally connected to the slide frame. The second folding assembly has a second frame pivotally connected to the first frame. In use, the first stage drive mechanism is operated to drive the first frame to pivot relative to the slide frame and the second stage drive mechanism is operated to drive the second frame to pivot relative to the first frame. Therefore, the legs of a sitter can be stretched and placed on the folding assemblies so as to enhance comfort and minimize fatigue. | 11-28-2013 |
20150021969 | FOLDABLE LEG REST - A foldable leg rest has a seat, a first folding frame and a first stage drive mechanism. The first folding frame is pivotally connected to the seat. The first stage drive mechanism includes two angle adjusters, two first stage DC motors and a drive rod. Each of the angle adjusters is disposed between one of opposite sides of the seat and one of opposite sides of the first folding frame. The first stage DC motors are respectively disposed on the sides of the seat. The drive rod is connected between the angle adjusters. In use, the first stage DC motors are actuated to drive the drive rod and the angle adjusters such that the first folding frame is pivoted relative to the seat. | 01-22-2015 |
20150375639 | ROTATABLE VEHICLE SEAT FRAME AND A ROTATABLE VEHICLE SEAT FRAME ASSEMBLY - A rotatable vehicle seat frame has a base bracket, a stand, a seat bracket and a back support bracket in sequence from up to down. A bottom sliding mechanism is mounted between the base bracket and the stand. A top sliding mechanism is mounted between the stand and the seat bracket. An angle-adjusting mechanism is mounted between the seat bracket and the back support bracket. The mechanisms mentioned above enable the rotatable vehicle seat frame to be rotated and transformed between a passenger-mode and a cargo-mode. Multiple rotatable vehicle seat frames with a frame and an elevatable desk form a rotatable vehicle seat frame assembly to be further applied in various kinds of vehicles. | 12-31-2015 |
Patent application number | Description | Published |
20140264924 | APPARATUS AND METHOD FOR MITIGATING DYNAMIC IR VOLTAGE DROP AND ELECTROMIGRATION AFFECTS - An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit. | 09-18-2014 |
20150095869 | METHOD OF MAKING SEMICONDUCTOR DEVICE AND A CONTROL SYSTEM FOR PERFORMING THE SAME - A method of making a semiconductor device includes arranging a first cell and a second cell, determining, by a processor, a first pattern density of a first cell, determining a second pattern density of a second cell, determining a pattern density gradient from the first pattern density to the second pattern density, determining whether the pattern density gradient exceeds a pattern density gradient threshold, and indicating a design change if the pattern density gradient exceeds than the pattern density gradient threshold. | 04-02-2015 |
20150161318 | METHOD OF MAKING SEMICONDUCTOR DEVICE AND SYSTEM FOR PERFORMING THE SAME - A method of making a semiconductor device includes determining, by a processor, a first pattern density of a first region, determining a second pattern density of a second region, determining a pattern density gradient from the first region to the second region, determining whether the pattern density gradient exceeds a pattern density gradient threshold and performing a placement or a routing of the semiconductor device if the pattern density gradient is less than or equal to the pattern density gradient threshold. | 06-11-2015 |