| Patent application number | Description | Published |
|---|
| 20100110807 | Bitline Leakage Detection in Memories - An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage. | 05-06-2010 |
| 20100208536 | Structure and Methods for Measuring Margins in an SRAM bit - Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, methods for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array architecture and circuit design. | 08-19-2010 |
| 20100232242 | Method for Constructing Shmoo Plots for SRAMS - A method of preparing Shmoo plots where both the number of failures and also the failure type is specified at each test voltage measurement point. A method that uses the operational SRAM array circuitry to determine the type of failure that may have occurred at each test voltage measurement point. | 09-16-2010 |
| 20110051539 | Method and structure for SRAM VMIN/VMAX measurement - A parametric test circuit is disclosed (FIG. | 03-03-2011 |
| 20110051540 | Method and structure for SRAM cell trip voltage measurement - A parametric test circuit is disclosed (FIG. | 03-03-2011 |
| 20110158017 | METHOD FOR MEMORY CELL CHARACTERIZATION USING UNIVERSAL STRUCTURE - A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first storage node set, a second storage node set, a set of other nodes, and a set of circuit elements each having a plurality of terminals, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type. The method further includes conducting a circuit element test on a circuit element in the set of circuit elements, where in the circuit element test the first and second supply nodes are not connected together, each terminal of the circuit element is directly forced with an electrical quantity, and an electrical quantity is directly measured from a terminal of the circuit element. Further, the method includes conducting at least one of a static noise margin test or a full cell test on the memory base cell. | 06-30-2011 |
| 20110158018 | Structure and Methods for Measuring Margins in an SRAM Bit - Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, methods for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array architecture and circuit design. | 06-30-2011 |
| 20110299349 | Margin Testing of Static Random Access Memory Cells - A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float during memory operations. The various tests are performed by precharging the bit lines for a column, then floating the bit lines, and while the bit lines are floating, pulsing the word lines of one or more selected cells to cause the voltage on one of the bit lines to discharge. The discharged bit line voltage is then applied to another cell, which is then read in a normal read operation to determine whether its state changed due to the discharged bit line voltage. The memory can be characterized for cell stability, write margin, and read current margin in this manner; the method can also be adapted into a manufacturing margin screen, or used in failure analysis. | 12-08-2011 |
