Wachnik
Richard A. Wachnik, Hopewell Junction, NY US
Patent application number | Description | Published |
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20140027851 | BODY CONTACTS FOR FET IN SOI SRAM ARRAY - Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N−, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P−) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown. | 01-30-2014 |
Richard A. Wachnik, Mount Kisco, NY US
Patent application number | Description | Published |
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20090295402 | VOLTAGE ISLAND PERFORMANCE/LEAKAGE SCREEN MONITOR FOR IP CHARACTERIZATION - A method is provided for characterizing performance of a chip having at least one voltage island and at least one performance screen ring oscillator (PSRO). An on-chip performance monitor (OCPM) is incorporated on the voltage island. Performance measurements of the voltage island are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) is compared to the performance measurements of the on-chip performance monitor (OCPM) to determine a systematic offset due to the voltage island. Performance models are adjusted using the systematic offset due to the voltage island. | 12-03-2009 |
Richard Andre Wachnik, Mount Kisco, NY US
Patent application number | Description | Published |
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20090200642 | HIGHLY TUNABLE METAL-ON-SEMICONDUCTOR TRENCH VARACTOR - An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper electrode comprising a top plate portion and a plurality of extension portions into the array of trenches. In a depletion mode, the bias condition across the dielectric layer depletes majority carriers within the top electrode, thus providing a low capacitance. In an accumulation mode, the bias condition attracts majority carriers toward the dielectric layer, providing a high capacitance. Thus, the trench metal-oxide-semiconductor (MOS) varactor provides a variable capacitance depending on the polarity of the bias. | 08-13-2009 |