Voon-Yew Thean, Austin US
Voon-Yew Thean, Austin, TX US
Patent application number | Description | Published |
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20080237635 | STRUCTURE AND METHOD FOR STRAINED TRANSISTOR DIRECTLY ON INSULATOR - A semiconductor device ( | 10-02-2008 |
20080258219 | Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer - A semiconductor device is provided which comprises a semiconductor layer ( | 10-23-2008 |
20090286387 | Modulation of Tantalum-Based Electrode Workfunction - A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer ( | 11-19-2009 |
20090289280 | Method for Making Transistors and the Device Thereof - A semiconductor process and apparatus includes forming <100> channel orientation PMOS transistors ( | 11-26-2009 |
20090291540 | CMOS Process with Optimized PMOS and NMOS Transistor Devices - A semiconductor process and apparatus includes forming NMOS and PMOS transistors ( | 11-26-2009 |
20100027355 | PLANAR DOUBLE GATE TRANSISTOR STORAGE CELL - A semiconductor device suitable for use as a storage cell includes a semiconductor body having a top surface and a bottom surface, a top gate dielectric overlying the semiconductor body top surface, an electrically conductive top gate electrode overlying the top gate dielectric, a bottom gate dielectric underlying the semiconductor body bottom surface, an electrically conductive bottom gate electrode underlying the bottom gate dielectric, and a charge trapping layer. The charge trapping layer includes a plurality of shallow charge traps, adjacent the top or bottom surface of the semiconductor body. The charge trapping layer may be of aluminum oxide, silicon nitride, or silicon nanoclusters. The charge trapping layer may located positioned between the bottom gate dielectric and the bottom surface of the semiconductor body. | 02-04-2010 |
20100078687 | Method for Transistor Fabrication with Optimized Performance - A semiconductor process and apparatus includes forming <100> channel orientation CMOS transistors ( | 04-01-2010 |
20100171180 | METHOD FOR PFET ENHANCEMENT - A semiconductor process and apparatus includes forming PMOS transistors ( | 07-08-2010 |
20100230756 | SEMICONDUCTOR DEVICE WITH SELECTIVELY MODULATED GATE WORK FUNCTION - A semiconductor device is provided which comprises a semiconductor layer ( | 09-16-2010 |