Volkerink
Eric Volkerink, Cupertino, CA US
Patent application number | Description | Published |
---|---|---|
20150370248 | System, Methods and Apparatus Using Virtual Appliances in a Semiconductor Test Environment - In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of hardware resources. Each virtual set of hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance. | 12-24-2015 |
Erik Volkerink, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20080252330 | METHOD AND APPARATUS FOR SINGULATED DIE TESTING - In accordance with one embodiment of the invention, a method of singulated die testing can be implemented. This can be implemented by obtaining a wafer and singulating the dies into individual die pieces. The singulated dies can be arranged in a separated testing arrangement and can even combine dies from multiple wafers as part of the combined arrangement. Then, testing can be implemented on the combined test arrangement. | 10-16-2008 |
Erik Volkerink US
Patent application number | Description | Published |
---|---|---|
20080235537 | System and method for electronic testing of multiple memory devices - A testing device may include a memory controller managing a transfer of data; and a plurality of interface boards. Each interface board includes a controller buffer. Each controller buffer transfers data between the memory controller and at least one memory module. The memory controller tests the at least one memory module. The testing device is operable to test the at least one memory module independent of an operating rate of the at least one memory module. The memory controller receives operating data of the at least one memory module. | 09-25-2008 |
Erik Volkerink, Palo Alto, CA US
Patent application number | Description | Published |
---|---|---|
20090144007 | System and method for electronic testing of devices - A system and method electronically tests devices. The method comprises receiving a first testing model including a first plurality of parameters and acceptable limits for the first plurality of parameters; receiving a second testing model including a second plurality of parameters and acceptable limits for the second plurality of parameters; receiving a first value for a first parameter from the first plurality of parameters, the first parameter at least partially affecting a second parameter from the second plurality of parameters; determining a second value for the second parameter based on the first value; determining if the first value is within the acceptable limits for the first parameter; determining if the second value is within the acceptable limits for the second parameter; and providing an indication when at least one of the first and second values is outside the acceptable limits for a corresponding one of the first and second parameters. | 06-04-2009 |
20140002121 | SYSTEM AND METHOD FOR ELECTRONIC TESTING OF PARTIALLY PROCESSED DEVICES | 01-02-2014 |
20140070828 | METHOD AND APPARATUS FOR MASSIVELY PARALLEL MULTI-WAFER TEST - Disclosed herein is a cost effective, efficient, massively parallel multi-wafer test cell. Additionally, this test cell can be used for both single-touchdown and multiple-touchdown applications. The invention uses a novel “split-cartridge” design, combined with a method for aligning wafers when they are separated from the probe card assembly, to create a cost effective, efficient multi-wafer test cell. A “probe-card stops” design may be used within the cartridge to simplify the overall cartridge design and operation. | 03-13-2014 |
Erik Volkerink, Saratoga, CA US
Patent application number | Description | Published |
---|---|---|
20140236527 | CLOUD BASED INFRASTRUCTURE FOR SUPPORTING PROTOCOL RECONFIGURATIONS IN PROTOCOL INDEPENDENT DEVICE TESTING SYSTEMS - A method for performing tests using automated test equipment (ATE) is presented. The method comprises obtaining a protocol selection for programming a programmable tester module using a graphical user interface (GUI). It further comprises accessing a configuration file associated with a protocol from a remote computer through a network. Subsequently, it comprises configuring a programmable tester module with a communication protocol for application to at least one device under test (DUT) using the configuration file. Finally, it comprises transmitting instructions to the programmable tester module for executing a program flow, wherein the program flow comprises a sequence of tests for testing the at least one DUT, and receiving results for those tests from the programmable tester module. | 08-21-2014 |
Erik H. Volkerink, Palo Alto, CA US
Patent application number | Description | Published |
---|---|---|
20130138383 | SOLUTION FOR FULL SPEED, PARALLEL DUT TESTING - A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmed to provide test patterns and an interface to at least one device under test (DUT). The system also includes a connection to the at least one DUT, wherein the connection is coupled directly between the configurable IC and the at least one DUT. | 05-30-2013 |
Erik H. Volkerink, Cupertino, CA US
Patent application number | Description | Published |
---|---|---|
20140189430 | SYSTEM, METHODS AND APPARATUS USING VIRTUAL APPLIANCES IN A SEMICONDUCTOR TEST ENVIRONMENT - In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of the hardware resources. Each virtual set of the hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance. | 07-03-2014 |
Erik H. Volkerink, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20110145645 | TEST SYSTEM AND METHOD FOR TESTING ELECTRONIC DEVICES USING A PIPELINED TESTING ARCHITECTURE - A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction. | 06-16-2011 |
Hendrik J. Volkerink, Palo Alto, CA US
Patent application number | Description | Published |
---|---|---|
20150238819 | EXERCISE EQUIPMENT WITH IMPROVED USER INTERACTION - Methods and systems are presented for accepting inputs into a treadmill or other exercise equipment to control functions of the treadmill or exercise equipment. An exercise control system can receive gestures and other inputs. The exercise control system can also obtain information about the user of the exercise control system and information about the environment in which the exercise equipment is operating. Based on the input and the other information, the exercise control system can modify or improve the performance or execution of user interface and functions of the exercise equipment. The changes make the user interfaces and/or functions user-friendly and intuitive. | 08-27-2015 |
Hendrik Jan (erik) Volkerink, Palo Alto, CA US
Patent application number | Description | Published |
---|---|---|
20120191402 | FLEXIBLE STORAGE INTERFACE TESTER WITH VARIABLE PARALLELISM AND FIRMWARE UPGRADEABILITY - A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmable to provide test patterns for use in automated test equipment. The configurable IC includes a configurable interface core that is programmable to provide functionality of one or more protocol based interfaces for a device under test (DUT) and is programmable to interface with the DUT. The system also includes a connection configurable to couple the configurable IC to the DUT. | 07-26-2012 |