Patent application number | Description | Published |
20090175395 | DATA ALIGNMENT METHOD FOR ARBITRARY INPUT WITH PROGRAMMABLE CONTENT DESKEWING INFO - In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams. | 07-09-2009 |
20100054386 | METHODS AND APPARATUS FOR SERIALIZER/DESERIALIZER TRANSMITTER SYNCHRONIZATION - Methods and apparatus are provided for serializer/deserializer transmitter synchronization. A plurality of channels are synchronized in one or more serializer/deserializer devices by generating a synchronization request in one or more of the channels; generating an enable signal in response to the synchronization request; and generating a gated synchronization signal for only one or more periods of a synchronization signal in response to the enable signal. The gated synchronization signal can optionally be deasserted after the one or more periods of a synchronization signal. | 03-04-2010 |
20100195777 | METHOD AND APPARATUS FOR IMPROVING LINEARITY IN CLOCK AND DATA RECOVERY SYSTEMS - Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal. | 08-05-2010 |
20100220776 | METHODS AND APPARATUS FOR PSEUDO ASYNCHRONOUS TESTING OF RECEIVE PATH IN SERIALIZER/DESERIALIZER DEVICES - Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock. | 09-02-2010 |
20100290513 | METHOD AND APPARATUS FOR INTEGRAL STATE INITIALIZATION AND QUALITY OF LOCK MONITORING IN A CLOCK AND DATA RECOVERY SYSTEM - Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied. | 11-18-2010 |
20110274143 | SPREAD SPECTRUM CLOCK SIGNAL GENERATOR METHOD AND SYSTEM - A system and method for generating a spread spectrum clock signal with a constant ppm offset as a function of a repetition number. A phase interpolator can be configured in association with of a phase-locked loop circuit in order to provide a phase movement from a bit clock generated by the PLL circuit. A repetition number divider computes the repetition number for each time slot in a piece-wise SSC modulation profile. A noise shaping modulator can be employed for modulating a fractional part associated with the repetition number. A repetition counter and a phase accumulator receives an integer part of the repetition number and counts unit interval clock periods equal to a sum of integer and the sigma-delta modulated fractional parts of the repetition number. The phase accumulator can be incremented and/or decremented based on the sign of the spread spectrum direction. | 11-10-2011 |
20120027073 | METHODS AND APPARATUS FOR ADAPTATION OF CONTINUOUS TIME-DECISION FEEDBACK EQUALIZERS WITH PROGRAMMABLE ADAPTATION PATTERNS - Methods and apparatus are provided for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns. A continuous time-decision feedback equalizer is adapted by obtaining at least one programmable signature pattern that triggers adaptation of one or more of a pole and a gain of the continuous time-decision feedback equalizer; detecting the at least one programmable signature pattern in an incoming signal; and adapting one or more of the pole and the gain of the continuous time-decision feedback equalizer when the at least one programmable signature pattern is detected in the incoming signal. The programmable signature pattern can be selected to ensure an unambiguous direction of change in an error sample when a corresponding one of the pole and the gain are modified. | 02-02-2012 |
20120257693 | CDR WITH SIGMA-DELTA NOISE-SHAPED CONTROL - In described embodiments, a receiver includes a clock and data recovery (CDR) module with a voltage control oscillator (VCO) and a Sigma-Delta modulator in an integral loop control of the VCO. Providing finer resolution by the Sigma-Delta modulator reduces quantization noise in the integral control loop when compared to a loop without a Sigma-Delta modulator in the integral loop. Sigma-Delta modulation within the integral loop control of a VCO-based CDR reduces effective quantization of the VCO integral word control, allowing the proportional loop control compensation to i) reduce effective quantization of the VCO integral word control and, ii) enhance receiver jitter tolerance in presence of periodic-jitter, serial data whose frequency is offset from the nominal rate and serial data whose nominal frequency is modulated by a spread spectrum clock. | 10-11-2012 |
20120287983 | METHODS AND APPARATUS FOR PSEUDO ASYNCHRONOUS TESTING OF RECEIVE PATH IN SERIALIZER/DESERIALIZER DEVICES - Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock. | 11-15-2012 |
20130009679 | BANG-BANG PHASE DETECTOR WITH HYSTERESIS - In described embodiments, a clock alignment system with a digital bang-bang phase detector (BBPD) employs digitally implemented hysteresis. A first BBPD is employed for a phase control loop that compares the phases from two different clock domain sources, where one clock domain source is used as a reference clock for the phase control loop. A second BBPD with delayed reference clock is employed to resolve ambiguous phase relations seen by the first BBPD. An initial state of a BBPD vector, defined as a vector of current values of the first BBPD and the second BBPD, is examined. Based on the initial and subsequent states of the BBPD vector, the non-reference clock is permitted to naturally move to a lock state through action of the phase control loop, or forced to have its phase rotate clockwise or counterclockwise to reach the lock state. | 01-10-2013 |
20130070835 | CDR WITH DIGITALLY CONTROLLED LOCK TO REFERENCE - In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation. | 03-21-2013 |
20130142245 | PATTERN DETECTOR FOR SERIALIZER-DESERIALIZER ADAPTATION - In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze. | 06-06-2013 |
20130282995 | ALIGNMENT FOR MULTIPLE FIFO POINTERS - In described embodiments, a multiple first-in, first-out buffer pointers (multi-FIFO pointers) alignment system includes synchronization circuitry to align multiple FIFO buffer operations. A FIFO read clock stoppage signal is generated by master logic that stops the read clock shared by all the transmit channels and then re-starts the read clock to align them. The FIFO read clock stoppage signal is applied to the read clock of all FIFOs which need to be aligned and, when rate change is needed, the FIFO read clock stoppage signal suspends the read clock, causing local write and read pointers to be reset. After the FIFO read clock stoppage signal is de-asserted, the read clock starts to all FIFOs concurrently, thereby aligning the channels. | 10-24-2013 |
20140023131 | METHODS AND APPARATUS FOR ADAPTING TRANSMITTER EQUALIZATION COEFFICIENTS BASED ON RECEIVER GAIN ADAPTATION - Methods and apparatus are provided for adapting transmitter equalization coefficients based on receiver gain adaptation. Equalization coefficients of a transmitter that communicates over a channel with a receiver are adapted by determining if a gain value for an amplifier in the receiver is within a limit of the amplifier; and preventing one or more adjustments to the transmitter equalization coefficients if the gain value does not satisfy the upper or lower limit of the amplifier. The gain adjustments comprise, for example, up and down requests for the transmitter equalization coefficients. One or more enable flags can optionally be set based on whether the gain value is within the limit of the amplifier. | 01-23-2014 |
20140097878 | SERIALIZER-DESERIALIZER CLOCK AND DATA RECOVERY GAIN ADJUSTMENT - In described embodiments, a VCO based CDR for a SerDes device includes a phase detector, a VCO responsive to a first control signal and a second control signal and generating an output signal, a frequency calibration module configured to calibrate the frequency of the output signal by performing a coarse calibration and a subsequent fine calibration, a gear shifting control module controlling a gain, change of the first and second control signals in time, and a look-up table created by fine calibration values generated from the frequency calibration module, wherein the programmed variable gain of the gear shifting control module is calculated by a calculation circuit employing the fine calibration values stored in the look-up table, the calculation of the calculation circuit adjusts gear shifting down, and adjusts a gear shifting gain, and adjusting an overall CDR gain over a VCO control curve. | 04-10-2014 |
20140098844 | JOINT TRANSMITTER AND RECEIVER GAIN OPTIMIZATION FOR HIGH-SPEED SERIAL DATA SYSTEMS - Embodiments of the present invention allow for adjustment of transmitter amplitude during joint transmitter (TX) and receiver (RX) equalization. During joint TX and RX adaptation, when the receiver requires a gain update, the receiver gain update is masked above or below a preset range. The RX gain update (instruction) is encoded into a transmitter amplitude update (instruction) transferred through back channel communication. The translation of RX gain to TX amplitude update is performed after the RX gain reaches a specified range. Such masking, encoding and translation reserves a certain amount RX gain range to account for RX gain variation due to process, voltage, and temperature (PVT) changes over time, and also to offer better linear equalization in the receiver over a constrained VGA bandwidth. | 04-10-2014 |
20140132320 | LOSS OF LOCK DETECTOR FOR CLOCK AND DATA RECOVERY SYSTEM - An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values. | 05-15-2014 |