Patent application number | Description | Published |
20130080493 | MODULAR EXPONENTIATION WITH PARTITIONED AND SCATTERED STORAGE OF MONTGOMERY MULTIPLICATION RESULTS - Embodiments of techniques and systems for side-channel-protected modular exponentiation are described. In embodiments, during a modular exponentiation calculation, Montgomery Multiplication (“MM”) results are produced. These MM results are scattered through a table for storage, such that storage of the values may not lead to discovery of a secret exponent value by a spy process through a side-channel attack. The scattering may be performed in order to reduce a number of per-result memory operations performed during each MM result storage or retrieval. In embodiments, a window size of 4 may be used in the modular exponentiation, along with partitioning of the MM result into 32-bit partition values which are scattered with offsets of 64-bytes. In embodiments, while use of a window size of 4 may result in additional MM calculations during modular exponentiation than other window sizes, the reduction in memory operations may provide a positive performance offset. | 03-28-2013 |
20130297664 | NUMBER SQUARING COMPUTER-IMPLEMENTED METHOD AND APPARATUS - Embodiments of the present disclosure describe computer-implemented methods, computer-readable media and computer system associated with big number squaring. A computer-implemented method to square a number x may include storing a t-digit vector representation of x in t b-bit registers of a processor. A 2t-digit intermediate vector may be generated and stored in 2t b-bit registers of the processor, using x stored in said t b-bit registers. A value stored in at least one of the t b-bit or 2t b-bit registers may be shifted to the left by n. n may be an integer at least equal to 1. At some point after the shifting, w, square of the number x, may be represented by the 2t-digit result vector stored in the 2t b-bit registers. Other embodiments may be described and/or claimed. | 11-07-2013 |
20130301826 | SYSTEM, METHOD, AND PROGRAM FOR PROTECTING CRYPTOGRAPHIC ALGORITHMS FROM SIDE-CHANNEL ATTACKS - A system for protecting algorithms from side-channel attacks includes a digital processor having a first register, a second register, and a third register; an execution unit; and a processing unit. The execution unit executes an iterative loop for computing a value of a variable and sets a value of the first register based on either an operation or an instruction (or both) within the iterative loop. The processing unit stores the computed value of the variable in the second register and stores a predefined constant in the third register. Side-channel protection may also be provided by a method, a processor, and a program stored on a computer-readable medium. | 11-14-2013 |
20130332707 | SPEED UP BIG-NUMBER MULTIPLICATION USING SINGLE INSTRUCTION MULTIPLE DATA (SIMD) ARCHITECTURES - A processing apparatus may be configured to include logic to generate a first set of vectors based on a first integer and a second set of vectors based on a second integer, logic to calculate sub products by multiplying the first set of vectors to the second set of vectors, logic to split each sub product into a first half and a second half and logic to generate a final result by adding together all first and second halves at respective digit positions. | 12-12-2013 |
20130332742 | SPEED UP SECURE HASH ALGORITHM (SHA) USING SINGLE INSTRUCTION MULTIPLE DATA (SIMD) ARCHITECTURES - A processing apparatus may comprise logic to preprocess a message according to a selected secure hash algorithm (SHA) algorithm to generate a plurality of message blocks, logic to generate hash values by preparing message schedules in parallel using single instruction multiple data (SIMD) instructions for the plurality of message blocks and to perform compression in serial for the plurality of message blocks, and logic to generate a message digest conforming to the selected SHA algorithm. | 12-12-2013 |
20130332743 | SPEED UP SECURE HASH ALGORITHM (SHA) USING SINGLE INSTRUCTION MULTIPLE DATA (SIMD) ARCHITECTURES - A processing apparatus comprises logic to, according to a selected secure hash algorithm (SHA) algorithm, generate hash values by preparing message schedules for a plurality of message blocks in parallel using single instruction multiple date (SIMD) instructions and performing compression in serial, and logic to generate a message digest conforming to the secure hash algorithm (SHA) algorithm. | 12-12-2013 |
20140006469 | VECTOR MULTIPLICATION WITH OPERAND BASE SYSTEM CONVERSION AND RE-CONVERSION | 01-02-2014 |
20140006755 | VECTOR MULTIPLICATION WITH ACCUMULATION IN LARGE REGISTER SPACE | 01-02-2014 |