Visokay, US
Mark Visokay, Richardson, TX US
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20080290427 | USE OF DOPANTS TO PROVIDE LOW DEFECT GATE FULL SILICIDATION - The invention provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming an NMOS gate structure over a substrate, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode. The method further includes forming n-type source/drain regions within the substrate proximate the NMOS gate structure, and forming a metal alloy layer over the NMOS gate electrode. The method additionally includes incorporating the metal alloy into the NMOS gate electrode to form an NMOS gate electrode fully silicided with the metal alloy. | 11-27-2008 |
20080290428 | USE OF ALLOYS TO PROVIDE LOW DEFECT GATE FULL SILICIDATION - The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the layer of gate dielectric material is positioned over a substrate. This method further includes patterning the layer of gate electrode material and the layer of gate dielectric material into an NMOS gate structure, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode. This method further includes forming n-type source/drain regions within the substrate proximate the NMOS gate structure, and siliciding the NMOS gate electrode to form a silicided gate electrode. This method additionally includes placing a p-type dopant within the layer of gate electrode material or the NMOS gate electrode prior to or concurrently with siliciding. | 11-27-2008 |
20080293193 | USE OF LOW TEMPERATURE ANNEAL TO PROVIDE LOW DEFECT GATE FULL SILICIDATION - Provided is a method for manufacturing a semiconductor device that includes forming a gate structure over a substrate, wherein the gate structure includes a gate dielectric and a gate electrode. The method further includes forming a metal layer over the gate electrode, and forming a fully silicided gate electrode using the metal layer. The fully silicided gate electrode may be formed by subjecting the gate electrode to a first anneal in a presence of the metal layer to form a silicided gate electrode, wherein a maximum temperature of the first anneal does not exceed about 340° C. The fully silicided gate electrode may further be formed by removing any unreacted portions of the metal layer after the first anneal, and subjecting the silicided gate electrode to a second anneal to form the fully silicided gate electrode subsequent to the removing. A maximum temperature of the second anneal exceeds about 400° C. | 11-27-2008 |
20090057759 | MOS DEVICE AND PROCESS HAVING LOW RESISTANCE SILICIDE INTERFACE USING ADDITIONAL SOURCE/DRAIN IMPLANT - An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×10 | 03-05-2009 |
20100109089 | MOS DEVICE AND PROCESS HAVING LOW RESISTANCE SILICIDE INTERFACE USING ADDITIONAL SOURCE/DRAIN IMPLANT - An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×10 | 05-06-2010 |
Mark Robert Visokay, Wappingers Falls, NY US
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20100323486 | TRIPLE-GATE TRANSISTOR WITH REVERSE SHALLOW TRENCH ISOLATION - Example embodiments provide triple-gate semiconductor devices isolated by reverse shallow trench isolation (STI) structures and methods for their manufacture. In an example process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The example triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality. | 12-23-2010 |
20110097884 | METHOD TO ATTAIN LOW DEFECTIVITY FULLY SILICIDED GATES - A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes. | 04-28-2011 |
Mark Robert Visokay, Richardson, TX US
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20080268599 | STRUCTURE AND METHOD FOR A TRIPLE-GATE TRANSISTOR WITH REVERSE STI - Exemplary embodiments provide triple-gate semiconductor devices isolated by reverse STI structures and methodologies for their manufacture. In an exemplary process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The exemplary triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality. | 10-30-2008 |
20090068828 | DUAL WORK FUNCTION CMOS DEVICES UTILIZING CARBIDE BASED ELECTRODES - Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region. | 03-12-2009 |
Mark Robert Visokay, Dallas, TX US
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20130056811 | Hydrogen-Blocking Film for Ferroelectric Capacitors - An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH | 03-07-2013 |
20130309783 | HYDROGEN-BLOCKING FILM FOR FERROELECTRIC CAPACITORS - An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH | 11-21-2013 |
20140147940 | PROCESS-COMPATIBLE SPUTTERING TARGET FOR FORMING FERROELECTRIC MEMORY CAPACITOR PLATES - A sputtering target for a conductive oxide, such as SrRuO | 05-29-2014 |