Patent application number | Description | Published |
20140264563 | Field Effect Transistor Devices with Protective Regions - A transistor device includes a first conductivity type drift layer, a second conductivity type first region in the drift layer, a body layer having the second conductivity type on the drift layer including the first region, a source layer on the body layer, and a body contact region that extends through the source layer and the body layer and into the first region. The transistor device further includes a trench through the source layer and the body layer and extending into the drift layer adjacent the first region. The trench has an inner sidewall facing away from the first region. A gate insulator is on the inner sidewall of the trench, and a gate contact is on the gate insulator. | 09-18-2014 |
20140264564 | Field Effect Transistor Devices with Buried Well Protection Regions - A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator. | 09-18-2014 |
20140264579 | Field Effect Transistor Devices with Buried Well Regions and Epitaxial Layers - A method of forming a transistor device includes providing a drift layer having a first conductivity type and an upper surface, forming first regions in the drift layer and adjacent the upper surface, the first regions having a second conductivity type that is opposite the first conductivity type and being spaced apart from one another, forming a body layer on the drift layer including the source regions, forming spaced apart source regions in the body layer above respective ones of the first regions, forming a vertical conduction region in the body layer between the source regions, the vertical conduction region having the first conductivity type and defining channel regions in the body layer between the vertical conduction region and respective ones of the source regions, forming a gate insulator on the body layer, and forming a gate contact on the gate insulator. | 09-18-2014 |
20150021742 | Methods of Forming Junction Termination Extension Edge Terminations for High Power Semiconductor Devices and Related Semiconductor Devices - Methods of forming a power semiconductor device having an edge termination are provided in which the power semiconductor device that has a drift region of a first conductivity type is formed on a substrate. A junction termination extension is formed on the substrate adjacent the power semiconductor device, the junction termination extension including a plurality of junction termination zones that are doped with dopants having a second conductivity type. The junction termination zones have different effective doping concentrations. A dopant activation process is performed to activate at least some of the dopants in the junction termination zones. An electrical characteristic of the power semiconductor device is measured. Then, the junction termination extension is etched in order to reduce the effective doping concentration within the junction termination extension. | 01-22-2015 |
20150028350 | Controlled Ion Implantation Into Silicon Carbide Using Channeling And Devices Fabricated Using Controlled Ion Implantation Into Silicon Carbide Using Channeling - Methods of forming a semiconductor structure include the use of channeled implants into silicon carbide crystals. Some methods include providing a silicon carbide layer having a crystallographic axis, heating the silicon carbide layer to a temperature of about 300° C. or more, implanting dopant ions into the heated silicon carbide layer at an implant angle between a direction of implantation and the crystallographic axis of less than about 2°, and annealing the silicon carbide layer at a time-temperature product of less than about 30,000° C.-hours to activate the implanted ions. | 01-29-2015 |
20150041886 | VERTICAL POWER TRANSISTOR DEVICE - A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer. | 02-12-2015 |
20150048489 | EDGE TERMINATION TECHNIQUE FOR HIGH VOLTAGE POWER DEVICES - Embodiments of a semiconductor die having a semiconductor device implemented on the semiconductor die and an edge termination structure around a periphery of the semiconductor device and methods of fabricating the same are disclosed. In one embodiment, a semiconductor die includes a semiconductor device and an edge termination structure around a periphery of the semiconductor device, where the edge termination structure includes negative features (e.g., trenches and/or divots) that vary dose in a corresponding edge termination region to approximate a desired dose profile. In one embodiment, the desired dose profile is a substantially decreasing or substantially linearly decreasing dose from an edge of a main junction of the semiconductor device to an edge of the edge termination region. In this manner, electric field crowding at the edge of the main junction of the semiconductor device is substantially reduced, which in turn substantially improves a break-down voltage of the semiconductor device. | 02-19-2015 |
20150084062 | MONOLITHICALLY INTEGRATED VERTICAL POWER TRANSISTOR AND BYPASS DIODE - A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer. | 03-26-2015 |
20150084063 | SEMICONDUCTOR DEVICE WITH A CURRENT SPREADING LAYER - A semiconductor device includes a substrate, a drift layer over the substrate, a spreading layer over the drift layer, and a pair of junction implants in a surface of the spreading layer opposite the drift layer. An anode covers the surface of the spreading layer opposite the drift layer, and a cathode covers a surface of the substrate opposite the drift layer. By including the spreading layer, a better balance can be struck between the on state resistance of the semiconductor device and the peak electric field in the device, thereby improving the performance thereof. | 03-26-2015 |
20150084118 | SEMICONDUCTOR DEVICE INCLUDING A POWER TRANSISTOR DEVICE AND BYPASS DIODE - A semiconductor device includes a vertical FET device and a Schottky bypass diode. The vertical FET device includes a gate contact, a source contact, and a drain contact. The gate contact and the source contact are separated from the drain contact by at least a drift layer. The Schottky bypass diode is coupled between the source contact and the drain contact and monolithically integrated adjacent to the vertical FET device such that a voltage placed between the source contact and the drain contact is distributed throughout the drift layer by the Schottky bypass diode in such a way that a voltage across each one of a plurality of P-N junctions formed between the source contact and the drain contact within the vertical FET device is prevented from exceeding a barrier voltage of the respective P-N junction. | 03-26-2015 |
20150084119 | LAYOUT CONFIGURATIONS FOR INTEGRATING SCHOTTKY CONTACTS INTO A POWER TRANSISTOR DEVICE - A semiconductor device includes a vertical field-effect-transistor (FET) and a bypass diode. The vertical FET device includes a substrate, a drift layer formed over the substrate, a gate contact and a plurality of source contacts located on a first surface of the drift layer opposite the substrate, a drain contact located on a surface of the substrate opposite the drift layer, and a plurality of junction implants, each of the plurality of junction implants laterally separated from one another on the surface of the drift layer opposite the substrate and extending downward toward the substrate. Each of the one or more bypass diodes are formed by placing a Schottky metal contact on the first surface of the drift layer, such that each Schottky metal contact runs between two of the plurality of junction implants. | 03-26-2015 |
20150084125 | MONOLITHICALLY INTEGRATED VERTICAL POWER TRANSISTOR AND BYPASS DIODE - A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer. | 03-26-2015 |