Patent application number | Description | Published |
20080222430 | Protection of Secure Electronic Modules Against Attacks - A method and apparatus is disclosed for preventing the unintended retention of secret data caused by preferred state/burn in secure electronic modules. Sequentially storing the data, and its inverse on alternating clock cycles, and by actively overwriting it to destroy it, prevents SRAM devices from developing a preferred state. By encrypting a relatively large amount of secret data with a master encryption key, and storing said master key in this non-preferred state storage, the electronic module conveniently extends this protection scheme to a large amount of data, without the overhead of investing or actively erasing the larger storage area. | 09-11-2008 |
20080231311 | PHYSICALLY HIGHLY SECURE MULTI-CHIP ASSEMBLY - A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts. | 09-25-2008 |
20100217946 | INDIRECTLY-ACCESSED, HARDWARE-AFFINE CHANNEL STORAGE IN TRANSACTION-ORIENTED DMA-INTENSIVE ENVIRONMENTS - Embodiments of the invention provide a method, system, and computer program product for managing a computer memory system including a channel controller and a memory area. In one embodiment, the method comprises the channel controller receiving a request including a header and a payload, and separating said memory area into a working memory area and an auxiliary memory area. A copy of the header is deposited in the working memory area; and a full copy of the request, including a copy of the header and a copy of the payload, is deposited in the auxiliary memory area. The copy of the request in the auxiliary memory area is used to perform hardware operations; and the copy of the header in the working memory area is used to perform software operations. | 08-26-2010 |
20110106870 | SYSTEM AND A METHOD FOR PROVIDING NONDETERMINISTIC DATA - A system and method for providing non-deterministic data for processes executed by non-synchronized processor elements of a fault resilient system is discussed. The steps of the method comprise receiving a request for getting non-deterministic data from a requesting processor element; assigning non-deterministic data generated by an entropy source to the request; and supplying the non-deterministic data assigned to the request, to the requesting processor element. | 05-05-2011 |
20120117666 | MULTILAYER SECURING STRUCTURE AND METHOD THEREOF FOR THE PROTECTION OF CRYPTOGRAPHIC KEYS AND CODE - An arrangement for the protection of cryptographic keys and codes from being compromised by external tampering, wherein the arrangement is utilized within a multilayered securing structure. More particularly, there is provided a multilayered securing structure for the protection of cryptographic keys and codes, which may be subject to potential tampering when employed in computers and/or telecommunication systems. A method is provided for producing such multilayered securing structures within a modular substrate with the intent to protect cryptographic keys and codes which are employed in computers and/or telecommunication systems from the dangers of potential tampering or unauthorized access. | 05-10-2012 |
20120167097 | ADAPTIVE CHANNEL FOR ALGORITHMS WITH DIFFERENT LATENCY AND PERFORMANCE POINTS - A method for processing requests in a channel can include receiving a first request in the channel, running calculations on the first request in a processing time T | 06-28-2012 |
20120278905 | CONFIGURABLE INTEGRATED TAMPER DECTECTION CIRCUITRY - Tamper detection circuitry includes a first surface layer surrounding a protected memory, the first surface layer comprising a first plurality of conductive sections; a second surface layer surrounding the protected memory, the second surface layer comprising a second plurality of conductive sections; a programmable interconnect located inside the first surface layer, the programmable interconnect being connected to each conductive section by a plurality of conductive traces, the programmable interconnect being configured to group the conductive section of the first and second plurality of conductive sections into a plurality of circuits, each of the plurality of circuits having a different respective voltage; and a tamper detection module, the tamper detection module configured to detect tampering in the event that a conductive section that is part of a first circuit comes into physical contact with a conductive section that is part of a second circuit. | 11-01-2012 |
20130091346 | Code Updates in Processing Systems - A method for updating code images in a system includes booting a first image of a code with a sub-system processor, receiving a second image of the code, performing a security and reliability check of the second image of the code with the sub-system processor, determining whether the security and reliability check of the second image of the code is successful, storing the second image of the code in a first memory device responsive to determining that the security and reliability check of the second image of the code is successful, designating the second image of the code as an active image, and sending the second image of the code to a second memory device, the second memory device communicatively connected with the first memory device and a main processor. | 04-11-2013 |
20140115405 | INTEGRITY CHECKING INCLUDING SIDE CHANNEL MONITORING - A method for integrity checking for a cryptographic engine in a computing system includes monitoring a state of a side channel of the cryptographic engine during operation of the cryptographic engine by a side channel monitor; comparing the state of the side channel to a side channel model of the cryptographic engine to determine whether a mismatch exists between the state of the side channel and the side channel model; and based on a mismatch between the state of the side channel and the model of the side channel, indicating an error in the cryptographic engine. | 04-24-2014 |