Patent application number | Description | Published |
20100103003 | Method and Apparatus for Dithering in Multi-Bit Sigma-Delta Analog-to-Digital Converters - A multi-bit (M-bit, M>1) or multi-level (nlev levels, nlev>2, encoded on M bits where M=Floor(log2(nlev))) sigma-delta analog-to-digital converter (ADC) with a variable resolution multi-bit quantizer having its resolution (number of distinct output levels) and associated quantization thresholds changed for each voltage sample with a random or pseudo-random sequence N(n) to provide automatic dynamic dithering for removing undesired idle tones in the digital output of the sigma-delta ADC. The random integer numbers N(n) between 2 and nlev may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder. | 04-29-2010 |
20100103013 | Method and Apparatus for Dithering in Multi-Bit Sigma-Delta Digital-to-Analog Converters - A multi-bit (M-bit, M>1) Sigma-Delta digital-to-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M−N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital truncator or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder. | 04-29-2010 |
20100103014 | Multi-Level Feed-Back Digital-To-Analog Converter Using A Chopper Voltage Reference For A Switched Capacitor Sigma-Delta Analog-To-Digital Converter - A multi-bit digital-to-analog converter has a reference voltage generator generating a reference voltage with an offset voltage; a switched capacitor stage for generating a plurality of output voltages; and a switching sequencer controlling the switched capacitor stage operable to generate switching patterns for each output voltages, wherein each pattern has a charge phase and a transfer phase, and wherein for at least one output voltage the switching sequencer provides two switching patterns wherein each switching pattern contributes an offset of opposite polarity. | 04-29-2010 |
20110012767 | 2-Phase Gain Calibration And Scaling Scheme For Switched Capacitor Sigma-Delta Modulator - A sigma-delta modulator may have a plurality of capacitor pairs, a plurality of switches to couple any pair of capacitors from the plurality of capacitor pairs selectively to an input signal or a reference signal, and a control unit operable to control sampling through the switches to perform a charge transfer in two phases wherein any pair of capacitors can be selected to be assigned to the input signal or the reference signal, and wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically such that after a rotation cycle, each capacitor pair has been assigned a first predetermined number of times to the input signal, and has also been assigned a second predetermined number of times to the reference signal. | 01-20-2011 |
20110022878 | Configuring Multi-Bit Slave Addressing on a Serial Bus Using a Single External Connection - Unique addresses for a plurality of devices may be programmed through a single external connection (pin) on each device by using a one of a plurality of different analog voltage or current values on the single external pin in combination with a serial clock of a serial data bus for each device requiring a unique binary address. The unique binary address is stored in the device after detection of certain number of clocks on the serial data bus. Once the unique binary address has been stored in the device, the single external connection may be used for another purpose such as a multifunction external connection. This unique binary address may be retained by the device until a power-on-reset (POR) or general reset condition occurs. Address detection and address load commands on the serial bus may also perform the same address definition and storage functions. | 01-27-2011 |
20110163901 | 2-PHASE GAIN CALIBRATION AND SCALING SCHEME FOR SWITCHED CAPACITOR SIGMA-DELTA MODULATOR USING A CHOPPER VOLTAGE REFERENCE - A sigma-delta modulator has a chopper voltage reference providing a reference signal having a clock dependent offset voltage, a single-bit or a multi-bit digital-to-analog converter (DAC); a plurality of capacitor pairs; a plurality of switches to couple any capacitor pair to an input or reference signal; and a control unit controlling sampling through said switches to perform a charge transfer in two phases wherein any capacitor pair can be selected to be assigned to the input or reference signal, wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically, and wherein a DAC output value and a reference offset state define switching sequences wherein each switching sequence independently rotates said capacitor pairs and wherein at least one switching sequence is selected depending on a current DAC output value and a current reference offset state. | 07-07-2011 |
20110169672 | METHOD AND APPARATUS FOR DITHERING IN MULTI-BIT SIGMA-DELTA DIGITAL-TO-ANALOG CONVERTERS - A multi-bit (M-bit, M>1) Sigma-Delta digital-to-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M-N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital truncator or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder. | 07-14-2011 |
20120161994 | SWITCHED-CAPACITANCE GAIN AMPLIFIER WITH IMPROVED INPUT IMPEDANCE - A gain amplifier may have a differential amplifier with feedback capacitors; a switched input stage having first and second outputs coupled with the differential amplifier, and having: first and second capacitors, a first input receiving a first signal of a differential input signal; a second input receiving a second signal of the differential input signal; a first plurality of switches controlled by a first clock signal to connect the first terminals of the first capacitor with the first or second input, respectively and to connect the first terminals of the second capacitors with the second and first input, respectively; and a second plurality of switches controlled by a phase shifted clock signal to connect the second terminal of the first capacitor with a first or second input of the differential amplifier and connecting the second terminal of the second capacitor with the second or first input of the differential amplifier. | 06-28-2012 |
20130120032 | Analog Front End Device with Two-Wire Interface - An analog front end (AFE) device has at least one programmable analog-to-digital converter (ADC) and a serial interface switchable to operate in a bidirectional serial interface mode and in a unidirectional two wire serial interface mode, wherein the unidirectional two wire serial interface mode only uses a clock input and a data output signal line, wherein the ADC operates in the unidirectional two wire serial interface mode synchronous with a clock supplied to the clock input. | 05-16-2013 |
20140240155 | 2-Phase Switched Capacitor Flash ADC - An input stage for a switched capacitor analog-to-digital converter has a differential voltage input receiving an input voltage, a differential reference voltage input receiving a chopped reference voltage, a common voltage connection, and a differential output. A pair of input capacitors is coupled between the differential voltage input and the differential output and a pair of reference capacitors is coupled between the differential reference voltage input. A switching unit is controlled by a first and second phase operable during the first phase to connect a first terminal of the input capacitors with the common voltage connection and couple the first terminal of the reference capacitors with the inverted differential voltage reference; and during a second phase to connect the first terminal of the input capacitors with the differential input voltage and couple the first terminal of the reference capacitors with the non-inverted differential voltage reference | 08-28-2014 |
20140253227 | Integrated High Voltage Isolation Using Low Value Capacitors - High voltage rated isolation capacitors are formed on a face of a primary integrated circuit die. The isolation capacitors AC couple the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitors DC isolate the primary integrated circuit from the second integrated circuit die. Isolated power transfer from the first voltage domain to the second voltage domain is provided through the high voltage rated isolation capacitors with an AC oscillator or PWM generator. The AC oscillator voltage amplitude may be increased for an increase in power through the high voltage rated isolation capacitors, and a larger value capacitor in the second voltage domain may provide for peak current demand from circuits in the second voltage domain. | 09-11-2014 |
20140253354 | Multi-Level Capacitive DAC - A digital-to analog converter (DAC) of the charge transfer type can be used in a sigma delta modulator for generating N output levels, wherein an output level is defined by a respective amount of charge transferred by the DAC. The DAC has a first capacitor switch unit receiving a reference voltage and a first digital input value to transfer first output charges, at least one second capacitor switch unit receiving the reference voltage and a second digital input value, wherein an output of the second capacitor switch unit is coupled in parallel with an output of the first capacitor switch unit to generate a sum of first and second transferred output charges; and a sequencer controlling switches of the first and second capacitor switch units wherein switching sequences according to individual first and second digital input values are provided for every DAC input value to generate the N output levels. | 09-11-2014 |
20140253355 | 4N+1 Level Capacitive DAC Using N Capacitors - A digital-to analog converter (DAC) of the charge transfer type for use in a sigma delta modulator, includes a capacitor switch unit operable to generate a 4n+1 output levels, comprising: a plurality of second switching units for coupling first terminals of a plurality of reference capacitor pairs with either a positive or a negative reference signal; wherein the second terminals of the plurality of reference capacitor pairs are coupled in parallel, respectively; wherein for even transfers a single switching combination is provided to achieve linearity and wherein for odd transfers an average of different switching combinations is provided to achieve linearity; wherein an even transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd. | 09-11-2014 |
20140368365 | Quantization Noise Coupling Delta Sigma ADC with a Delay in the Main DAC Feedback - A delta-sigma modulator has a first summing point subtracting a first feedback signal from an input signal and forwarding a result to a transfer function, a second summing point adding an output signal from said transfer function to the input signal and subtracting a second feedback signal, a first integrator receiving an output signal from the second summing point, a quantizer receiving an output signal from the integrator and generating an output bitstream, and a digital-to-analog converter receiving the bitstream, wherein the first and second feedback signal are the output signal from said digital-to-analog converter delayed by a one sample delay. | 12-18-2014 |