Patent application number | Description | Published |
20090273023 | Segmented pillar layout for a high-voltage vertical transistor - In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. | 11-05-2009 |
20090315105 | High-voltage vertical transistor structure - In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 12-24-2009 |
20100065903 | High-voltage vertical transistor with a varied width silicon pillar - In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. | 03-18-2010 |
20100155773 | VTS insulated gate bipolar transistor - In one embodiment, a power transistor device comprises a substrate that forms a PN junction with an overlying buffer layer. The power transistor device further includes a first region, a drift region that adjoins a top surface of the buffer layer, and a body region. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. First and second field plates are respectively disposed in the first and second dielectric regions. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region. | 06-24-2010 |
20100155831 | Deep trench insulated gate bipolar transistor - In one embodiment, a power transistor device comprises a substrate of a first conductivity type that forms a PN junction with an overlying buffer layer of a second conductivity type. The power transistor device further includes a first region of the second conductivity type, a drift region of the second conductivity type that adjoins a top surface of the buffer layer, and a body region of the first conductivity type. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region. | 06-24-2010 |
20100159649 | Method of fabricating a deep trench insulated gate bipolar transistor - In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region. | 06-24-2010 |
20100301412 | Power integrated circuit device with incorporated sense FET - In one embodiment, a power integrated circuit device includes a main lateral high-voltage field-effect transistor (HVFET) and an adjacently-located lateral sense FET, both of which are formed on a high-resistivity substrate. A sense resistor is formed in a well region disposed in an area of the substrate between the HVFET and the sense FET. A parasitic substrate resistor is formed in parallel electrical connection with the sense resistor between the source regions of the HVFET and the sense FET. Both transistor devices share common drain and gate electrodes. When the main lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET. | 12-02-2010 |
20110042726 | High-voltage transistor device with integrated resistor - A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 02-24-2011 |
20110073942 | High-voltage transistor structure with reduced gate capacitance - In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer. | 03-31-2011 |
20110089476 | Checkerboarded high-voltage vertical transistor layout - In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. | 04-21-2011 |
20110140166 | Method of fabricating a deep trench insulated gate bipolar transistor - In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region. | 06-16-2011 |
20110233657 | High-voltage vertical transistor with a varied width silicon pillar - In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. | 09-29-2011 |
20120058607 | Method of fabricating a deep trench Insulated Gate Bipolar Transistor - In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region. | 03-08-2012 |
20120061720 | VTS insulated gate bipolar transistor - In one embodiment, a power transistor device comprises a substrate that forms a PN junction with an overlying buffer layer. The power transistor device further includes a first region, a drift region that adjoins a top surface of the buffer layer, and a body region. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. First and second field plates are respectively disposed in the first and second dielectric regions. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region. | 03-15-2012 |
20120061755 | Checkerboarded high-voltage vertical transistor layout - In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. | 03-15-2012 |
20120146105 | High-voltage transistor device with integrated resistor - A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 06-14-2012 |
20120273885 | High-Voltage Transistor Structure with Reduced Gate Capacitance - In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer. | 11-01-2012 |
20120280314 | Gate Pullback at Ends of High-Voltage Vertical Transistor Structure - In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 11-08-2012 |
20120306012 | Power Integrated Circuit Device With Incorporated Sense FET - In one embodiment, a power integrated circuit device includes a main lateral high-voltage field-effect transistor (HVFET) and an adjacently-located lateral sense FET, both of which are formed on a high-resistivity substrate. A sense resistor is formed in a well region disposed in an area of the substrate between the HVFET and the sense FET. A parasitic substrate resistor is formed in parallel electrical connection with the sense resistor between the source regions of the HVFET and the sense FET. Both transistor devices share common drain and gate electrodes. When the main lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET. | 12-06-2012 |
20120313140 | Method of Fabricating a Deep Trench Insulated Gate Bipolar Transistor - In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region. | 12-13-2012 |
20130187219 | High-Voltage Vertical Transistor With a Varied Width Silicon Pillar - In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. | 07-25-2013 |
20130207192 | Power Integrated Circuit with Incorporated Sense FET - In one embodiment, a power integrated circuit device includes a main lateral high-voltage field-effect transistor (HVFET) and an adjacently-located lateral sense FET, both of which are formed on a high-resistivity substrate. A sense resistor is formed in a well region disposed in an area of the substrate between the HVFET and the sense FET. A parasitic substrate resistor is formed in parallel electrical connection with the sense resistor between the source regions of the HVFET and the sense FET. Both transistor devices share common drain and gate electrodes. When the main lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET. | 08-15-2013 |
20130234243 | Checkerboarded High-Voltage Vertical Transistor Layout - In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 09-12-2013 |
20130320482 | High-Voltage Monolithic Schottky Device Structure - A semiconductor device includes a pillar formed on a substrate of the same conductivity type. The pillar has a vertical thickness that extends from a top surface down to the substrate. The pillar extends in first and second lateral directions in a loop shape. First and second dielectric regions are disposed on opposite lateral sides of the pillar, respectively. First and second conductive field plates are respectively disposed in the first and second dielectric regions. A metal layer is disposed on the top surface of the pillar, the metal layer forming a Schottky diode with respect to the pillar. When the substrate is raised to a high-voltage potential with respect to both the metal layer and the first and second field plates, the first and second field plates functioning capacitively to deplete the pillar of charge, thereby supporting the high-voltage potential along the vertical thickness of the pillar. | 12-05-2013 |
20140042533 | Segmented Pillar Layout for a High-Voltage Vertical Transistor - In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. | 02-13-2014 |