Patent application number | Description | Published |
20080251863 | HIGH-VOLTAGE RADIO-FREQUENCY POWER DEVICE - A high-voltage RF power device includes a plurality of serially connected transistors. Each transistor includes a gate finger disposed on a substrate, a gate dielectric layer, a drain structure disposed on one side of the gate finger, and an N+ source region on the other side of the gate finger. The drain structure includes an N+ doping region encompassed by a shallow trench isolation (STI) structure, and an N well directly underneath the STI structure and the N+ doping region. | 10-16-2008 |
20100099229 | METHOD FOR FORMING A THIN FILM RESISTOR - A method for forming a thin film resistor includes providing a substrate having a transistor region and a thin film resistor region defined thereon, sequentially forming a dielectric layer, a metal layer and a first hard mask layer on the substrate, patterning the first hard mask layer to form at least a thin film resistor pattern in the thin film resistor region, sequentially forming a polysilicon layer and a second hard mask layer on the substrate, patterning the second hard mask layer to form at least a gate pattern in the transistor region, and performing an etching process to form a gate and a thin film resistor respectively in the transistor region and the thin film resistor region. | 04-22-2010 |
20100109080 | PSEUDO-DRAIN MOS TRANSISTOR - A pseudo-drain MOS transistor is disclosed. The transistor includes a semiconductor substrate; a gate structure disposed on the semiconductor substrate; a source, a pseudo-drain, a drain, and a shallow trench isolation disposed in the semiconductor substrate, a p-well disposed in the semiconductor substrate and under the source and the gate structure; and an n-well disposed under the drain. The source and the pseudo-drain are disposed adjacent to two sides of the gate structure and the shallow trench isolation is disposed between the pseudo-drain and the drain, and the n-well is extended toward the pseudo-drain while not reaching the area below the gate structure. | 05-06-2010 |
20100200947 | DIE SEAL RING - A die seal ring disposed outside of a die region of a semiconductor substrate is disclosed. The die seal ring includes a first isolation structure, a second isolation structure, and at least one third isolation structure disposed between the first isolation structure and the second isolation structure; a plurality of first regions between the first isolation structure, the second isolation structure and the third isolation structure; a second region under the first region and the third isolation structure; and a third region under the first isolation structure. | 08-12-2010 |
20100320544 | METAL GATE TRANSISTOR AND RESISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor. | 12-23-2010 |
20100328022 | METHOD FOR FABRICATING METAL GATE AND POLYSILICON RESISTOR AND RELATED POLYSILICON RESISTOR STRUCTURE - An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection. | 12-30-2010 |
20110073957 | METAL GATE TRANSISTOR WITH RESISTOR - A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures. | 03-31-2011 |
20110171810 | METAL GATE TRANSISTOR AND RESISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor. | 07-14-2011 |
20120214284 | METHOD FOR FABRICATING METAL GATE TRANSISTOR AND POLYSILICON RESISTOR - An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection. | 08-23-2012 |
20140001518 | Integrated Circuit Devices with Well Regions and Methods for Forming the Same | 01-02-2014 |
20140042506 | Transistors, Methods of Manufacture Thereof, and Image Sensor Circuits - Transistors, methods of manufacturing thereof, and image sensor circuits are disclosed. In one embodiment, a transistor includes a buried channel disposed in a workpiece, a gate dielectric disposed over the buried channel, and a gate layer disposed over the gate dielectric. The gate layer comprises an I shape in a top view of the transistor. | 02-13-2014 |