Patent application number | Description | Published |
20080225601 | EEPROM MEMORY DEVICE WITH CELL HAVING NMOS IN A P POCKET AS A CONTROL GATE, PMOS PROGRAM/ERASE TRANSISTOR, AND PMOS ACCESS TRANSISTOR IN A COMMON WELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 09-18-2008 |
20080273392 | METHOD OF PROGRAMMING A SELECTED MEMORY CELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 11-06-2008 |
20080273401 | METHOD OF ERASING A BLOCK OF MEMORY CELLS - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 11-06-2008 |
20090014772 | EEPROM MEMORY CELL WITH FIRST-DOPANT-TYPE CONTROL GATE TRANSISTOR, AND SECOND-DOPANT TYPE PROGRAM/ERASE AND ACCESS TRANSISTORS FORMED IN COMMON WELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 01-15-2009 |
20110089420 | BACKSIDE ONLY CONTACT THIN-FILM SOLAR CELLS AND DEVICES, SYSTEMS AND METHODS OF FABRICATING SAME, AND PRODUCTS PRODUCED BY PROCESSES THEREOF - Systems, methods, devices, and products of processes consistent with the innovations herein relate to thin-film solar cells having contacts on the backside, only. In one exemplary implementation, there is provided a thin film device. Moreover, such device may comprise a substrate, and a layer of silicon or silicon-containing material positioned on a first side of the substrate, wherein the layer comprises a n-doped region and a p-doped region. In some exemplary implementations, the device may be fabricated such that the n-doped region and the p-doped region are formed on the backside surface of the layer to create an electrical structure characterized by a P-type anode and an N-type cathode forming a junction positioned along the backside surface of the layer. | 04-21-2011 |
20110089429 | SYSTEMS, METHODS AND MATERIALS INVOLVING CRYSTALLIZATION OF SUBSTRATES USING A SEED LAYER, AS WELL AS PRODUCTS PRODUCED BY SUCH PROCESSES - Systems, methods, and products of processes consistent with the innovations herein relate to aspects involving crystallization of layers on substrates. In one exemplary implementation, there is provided a method of fabricating a device. Moreover, such method may include placing a seed layer on a base substrate, covering the seed layer with an amorphous/poly material, and heating the seed layer/material to transform the material into crystalline form. | 04-21-2011 |
20110101364 | SYSTEMS, METHODS AND MATERIALS INCLUDING CRYSTALLIZATION OF SUBSTRATES VIA SUB-MELT LASER ANNEAL, AS WELL AS PRODUCTS PRODUCED BY SUCH PROCESSES - Systems, methods, and products of processes consistent with the innovations herein relate to aspects involving crystallization of layers on substrates. In one exemplary implementation, there is provided a method of fabricating a device. Moreover, such method may include placing an amorphous/poly material on a substrate and heating the material via a sub-melt laser anneal process to transform the material into crystalline form. | 05-05-2011 |
20110165721 | SYSTEMS, METHODS AND PRODUCTS INCLUDING FEATURES OF LASER IRRADIATION AND/OR CLEAVING OF SILICON WITH OTHER SUBSTRATES OR LAYERS - The present innovations relate to optical/electronic structures, and, more particularly, to methods and products consistent with composite structures for optical/electronic applications, such as solar cells and displays, composed of a silicon-containing material bonded to a substrate and including laser treatment. | 07-07-2011 |
20110306180 | Systems, Methods and Products Involving Aspects of Laser Irradiation, Cleaving, and/or Bonding Silicon-Containing Material to Substrates - Systems, methods and products by process are disclosed relating to structures and/or fabrication thereof as relating, for example, to optical/electronic applications such as solar cells and displays. In one exemplary implementation, there is provided a method of producing a composite structure. Moreover, the method may include engaging a silicon-containing material into contact with a surface of the substrate and irradiating/treating the silicon-containing piece with a laser. | 12-15-2011 |
20120018733 | Thin Film Solar Cells And Other Devices, Systems And Methods Of Fabricating Same, And Products Produced By Processes Thereof - Systems, methods, devices, and products of processes consistent with the innovations herein relate to thin-film solar cells and other devices. In one exemplary implementation, there is provided a thin film device. | 01-26-2012 |
20130083608 | 1T SMART WRITE - The threshold voltages of particular nonvolatile memory cells on a word line are selectively increased on a column by column (cell by cell) basis. A selective program is performed on some of the cells, and simultaneously a program inhibit on other of the cells, resulting in all of the cells having a threshold voltage that falls between a minimum acceptable value and a maximum acceptable value. | 04-04-2013 |
20130122629 | SYSTEMS, METHODS AND PRODUCTS INCLUDING FEATURES OF LASER IRRADIATION AND/OR CLEAVING OF SILICON WITH OTHER SUBSTRATES OR LAYERS - The present innovations relate to optical/electronic structures, and, more particularly, to methods and products consistent with composite structures for optical/electronic applications, such as solar cells and displays, composed of a silicon-containing material bonded to a substrate and including laser treatment. | 05-16-2013 |
20140021477 | SYSTEMS, METHODS AND MATERIALS INCLUDING CRYSTALLIZATION OF SUBSTRATES VIA SUB-MELT LASER ANNEAL, AS WELL AS PRODUCTS PRODUCED BY SUCH PROCESSES - Systems, methods, and products of processes consistent with the innovations herein relate to aspects involving crystallization of layers on substrates. In one exemplary implementation, there is provided a method of fabricating a device. Moreover, such method may include placing an amorphous/poly material on a substrate and heating the material via a sub-melt laser anneal process to transform the material into crystalline form. | 01-23-2014 |
20140197864 | Non-Volatile Latch Structures with Small Area for FPGA - A latch circuit and method includes providing a first tri-gate non-volatile device, providing a second tri-gate non-volatile device, coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device, erasing the first tri-gate non-volatile device, programming the second tri-gate non-volatile device, and latching an output node of the latch device to a logic state determined by respective thresholds of the first and second tri-gate non-volatile devices. Coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device can include direct coupling, or indirect coupling through a cross-coupled circuit. | 07-17-2014 |
20140239374 | EMBEDDED SONOS BASED MEMORY CELLS - Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric on the substrate and a charge-trapping layer on the tunneling dielectric; patterning the dielectric stack to form a gate stack of a NVM transistor of a memory device in a first region of the substrate while concurrently removing the dielectric stack from a second region of the substrate; and performing a gate oxidation process of a baseline CMOS process flow to thermally grow a gate oxide of a MOS transistor overlying the substrate in the second region while concurrently growing a blocking oxide overlying the charge-trapping layer. In one embodiment, Indium is implanted to form a channel of the NVM transistor. | 08-28-2014 |
20140264552 | NONVOLATILE MEMORY CELLS AND METHODS OF MAKING SUCH CELLS - A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel. Methods of forming such a memory cell are also disclosed. | 09-18-2014 |
20140301139 | Method to Reduce Program Disturbs in Non-Volatile Memory Cells - A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (V | 10-09-2014 |
20150041881 | Embedded SONOS Based Memory Cells - A memory device that includes a non-volatile memory (NVM) transistor which has an indium doped channel and a gate stack overlying the channel formed in a first region of a substrate and a metal-oxide-semiconductor (MOS) transistor formed in a second region of the substrate in which the gate oxide of the MOS and the oxide layer of the NVM transistor are formed concurrently. | 02-12-2015 |